L6717ATR datasheet(35/57 Pages) STMICROELECTRONICS

35 / 57 page

DocID024465 Rev 1

35/57

L6717A

Output voltage positioning

Output voltage positioning is performed by selecting the controller operative-mode (

SVI, PVI

and

V_FIX) and by programming the droop function and offset to the reference of both the

sections (See

Figure 10). The controller reads the current delivered by each section by

monitoring the voltage drop across the DCR inductors. The current (I

DROOP

/ I

DROOP_NB

)

sourced from the FB / NB_FB pin, directly proportional to the read current, causes the

related section output voltage to vary according to the external R

/ R

FB_NB

resistor so

implementing the desired load-line effect.

L6717A embeds a dual Remote-Sense Buffer to sense remotely the regulated voltage of

each Section without any additional external components. In this way, the output voltage

programmed is regulated compensating for board and socket losses. Keeping the sense

traces parallel and guarded by a power plane results in common mode coupling for any

picked-up noise.

Figure 10. Voltage positioning

1.2V

ROS

SCL/OS

CORE_REFERENCE

COMP

VSEN

FBG

To VDD_CORE

(Remote Sense)

CORE Protection

Monitor

from SVI DAC...

NB_REFERENCE

NB_FB

NB_COMP

NB_VSEN

NB_FBG

F_NB

FB_NB

To VDD_NB

(Remote Sense)

NB Protection

Monitor

from DAC...

Operative only when Power Manager I2C disabled

Offset from Power Manager I2C

(Active when enabled)

Clamp to 2.8V

max

L6717ATR データシート(PDF) 35 Page - STMicroelectronics

L6717ATR データシート(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

データシートダウンロード