STM32F398VE datasheet(16/151 Pages) STMICROELECTRONICS

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Functional overview

STM32F398VE

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DocID027227 Rev 2

Note:

The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Note:

For more details about the interconnect actions, please refer to the corresponding sections

in the STM32F398VEreference manual (RM0316).

3.9

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Table 3. STM32F398VE peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DAC1

Conversion triggers

DMA

Memory to memory transfer trigger

Compx

Comparator output blanking

COMPx

TIMx

Timer input: OCREF_CLR input, input capture

ADCx

TIMx

Timer triggered by analog watchdog

GPIO

RTCCLK

HSE/32

MC0

TIM16

Clock source used as input channel for HSI and

LSI calibration

CSS

CPU (hard fault)

COMPx

GPIO

TIM1, TIM8, TIM20

TIM15, 16, 17

Timer break

GPIO

TIMx

External trigger, timer break

ADCx

DAC1

Conversion external trigger

DAC1

COMPx

Comparator inverting input

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