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STM32L100RB データシート(PDF) 83 Page - STMicroelectronics |
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STM32L100RB データシート(HTML) 83 Page - STMicroelectronics |
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83 / 103 page  DocID024295 Rev 5 83/103 STM32L100C6 STM32L100R8/RB Electrical characteristics 90 fTRIG External trigger frequency Regular sequencer 12-bit conversions - - Tconv+1 1/fADC 6/8/10-bit conversions - - Tconv 1/fADC fTRIG External trigger frequency Injected sequencer 12-bit conversions - - Tconv+2 1/fADC 6/8/10-bit conversions - - Tconv+1 1/fADC RAIN Signal source impedance(3) -- - 50 κΩ tlat Injection trigger conversion latency fADC = 16 MHz 219 - 281 ns -3.5 - 4.5 1/fADC tlatr Regular trigger conversion latency fADC = 16 MHz 156 - 219 ns -2.5 - 3.5 1/fADC tSTAB Power-up time - - - 3.5 µs 1. The current consumption through VDDA is composed of two parameters: - one constant (max 1300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses. So, peak consumption is 1300+400 = 1700 µA and average consumption is 1300 + [(4 sampling + 2) /16] x 400 = 1450 µA at 1Msps 2. VSSA must be tied to ground. 3. See Table 55: Maximum source impedance RAIN max for RAIN limitations Table 53. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 54. ADC accuracy(1)(2) Symbol Parameter Test conditions Min(3) Typ Max(3) Unit ET Total unadjusted error 2.4 V ≤ VDDA ≤ 3.6 V fADC = 8 MHz, RAIN = 50 Ω TA = -40 to 85 ° C -2.5 4 LSB EO Offset error - 1 2 EG Gain error - 1.5 3.5 ED Differential linearity error - 1 2 EL Integral linearity error - 2 3 ENOB Effective number of bits 2.4 V ≤ VDDA ≤ 3.6 V fADC = 16 MHz, RAIN = 50 Ω TA = -40 to 85 ° C Finput =10 kHz 9.5 10 - bits SINAD Signal-to-noise and distortion ratio 59 62 - dB SNR Signal-to-noise ratio 60 62 - THD Total harmonic distortion - -72 -69 ENOB Effective number of bits 1.8 V ≤ VDDA ≤ 2.4 V fADC = 8 MHz or 4 MHz, RAIN = 50 Ω TA = -40 to 85 ° C Finput =10 kHz 9.5 10 - bits SINAD Signal-to-noise and distortion ratio 59 62 - dB SNR Signal-to-noise ratio 60 62 - THD Total harmonic distortion - -72 -69 |
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