AD6676EBZ datasheet(57/90 Pages) AD

57 / 90 page

Data Sheet

AD6676

Rev. D | Page 57 of 90

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

150

160

170

180

190

200

210

220

230

240

250

INPUT FREQUENCY (MHz)

fIN = 180MHz

(–1dBFS)

M = 2, N = –1 SPUR

@ –88dBc

M = 1, N = 0 SPUR

@ –81dBFS

NBW = 9.2kHz

Figure 137. Image Spur for fDATA_IQ = 200 MSPS (DEC_MODE = 3) Attributed to

M = 2, N = −1

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

150

160

170

180

190

200

210

220

230

240

250

INPUT FREQUENCY (MHz)

fIN = 180MHz

(–1dBFS)

M = 4, N = –1 SPUR

@ –96dBc

M = 1, N = 0 SPUR

@ –81dBFS

NBW = 9.2kHz

Figure 138. Reduction in Image Spur When fDATA_IQ is Reduced to 100 MSPS

IF pass band regions that remain free of any of these spurs exist

in the following regions for a swept input tone across its pass band:

(M − 0.5) × fDATA_IQ < IF Pass Band < M × fDATA_IQ

(16)

× fDATA_IQ < IF Pass Band < (M + 0.5) × fDATA_IQ

(17)

Note that because these spur free regions have a bandwidth of

0.5 × fDATA_IQ, it is often desirable to use a higher fDATA_IQ rate (that is,

lower decimation factor) to support larger IF bands. Figure 139

shows a spur free region swept SFDR less than −95 dBFS with

fDATA_IQ = 200 MSPS and BW = 100 MHz with the IF now centered

at 250 MHz. Selecting an IF situated at 350 MHz and BW =

100 MHz also produces similar results.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

200

210

220

230

240

250

260

270

280

290

300

INPUT FREQUENCY (MHz)

fIN = 238MHz

(–1dBFS)

NBW = 9.2kHz

Figure 139. Digital Induced Spurs for an IF That Is Centered Between fDATA_IQ

and 1.5 × fDATA_IQ with fDATA_IQ = 200 MSPS

PCB DESIGN GUIDELINES

The design of the PCB is critical in achieving the full performance

of the AD6676. The AD6676EBZ evaluation board, used for

characterizing the AD6676 ac performance, serves as an example of

a possible layout that uses 0.1 mm (4 mil) through-hole vias under

the device. Figure 140 shows the top side PCB layout of the region

surrounding the AD6676 where all the critical analog input/

outputs, digital input/outputs, and passive components reside.

An alternative top side layout is shown in Figure 141 that avoids

any through-hole vias under the device. Because this modified

layout resulted in only a slight degradation in IMD performance,

consider this layout option if via placement under the device is

not possible.

Note the following:



The PCB is a 6-layer board (1.6 mm thick) based on FR4

dielectric that avoids any expensive options, such as micro,

hidden or blind vias, thus allowing cost effective

manufacturing.



Critical analog and digital high speed signal paths are

routed on the first layer with controlled impedances. The

lower speed CMOS digital input/outputs are placed on the

back side sixth layer.



A single solid ground plane is used as the second layer

underneath the AD6676. The dielectric spacing is 8 mil

to establish controlled impedances with the critical signal

layer above.

The third and fourth layers are dedicated power planes used to

isolate the different AD6676 supply domains, and the fifth

layer is a solid ground plane. The dielectric spacing between

the second and third layer and the fourth and fifth layer is

3 mil to increase the distributed decoupling capacitance for

each supply domain.



Special consideration was given to via placement, ground fill,

and power supply plane layout to main low thermal and

electrical impedances.

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