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AD6676EBZ データシート(PDF) 81 Page - Analog Devices |
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AD6676EBZ データシート(HTML) 81 Page - Analog Devices |
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81 / 90 page  Data Sheet AD6676 Rev. D | Page 81 of 90 JESD204 RES2 Register Address: 0x1CC, Reset: 0x00, Name: RES2 Table 100. Bit Descriptions for RES2 Bits Bit Name Description Reset Access [7:0] RES2 0x00 RW JESD204 LID0 Register Address: 0x1D0, Reset: 0x00, Name: LID0 Table 101. Bit Descriptions for LID0 Bits Bit Name Description Reset Access [7:5] RESERVED 0x0 RW [4:0] LID0 Lane ID for Lane 0. 0x00 RW JESD204 LID1 Register Address: 0x1D1, Reset: 0x01, Name: LID1 Table 102. Bit Descriptions for LID1 Bits Bit Name Description Reset Access [7:5] RESERVED 0x0 RW [4:0] LID1 Lane ID for Lane 1. 0x01 RW JESD204 FCHK0 Register Address: 0x1D8, Reset: 0x44, Name: FCHK0 Table 103. Bit Descriptions for FCHK0 Bits Bit Name Description Reset Access [7:0] FCHK0 Checksum for Lane 0. 0x44 RW JESD204 FCHK1 Register Address: 0x1D9, Reset: 0x45, Name: FCHK1 Table 104. Bit Descriptions for FCHK1 Bits Bit Name Description Reset Access [7:0] FCHK1 Checksum for Lane 1. 0x45 RW Enable Lane FIFO Register Address: 0x1E0, Reset: 0x00, Name: EN_LFIFO Table 105. Bit Descriptions for EN_LFIFO Bits Bit Name Description Reset Access [7:1] RESERVED 0x00 RW 0 EN_LFIFO Lane FIFO Enable. Once the entire configuration of the framer has been completed, and the link is powered up, set this bit to start the lane FIFOs that manage the hand-off of data from the framer to the transmitter PHY. 0x0 RW |
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