AD6676EBZ datasheet(8/90 Pages) AD

8 / 90 page

AD6676

Data Sheet

Rev. D | Page 8 of 90

CLK± TO SYSREF± TIMING DIAGRAM

CLK+

CLK–

SYSREF+

SYSREF–

tSU_SR

tH_SR

Figure 2. SERDES CLK+ to SYSREF+ Timing

DIGITAL CMOS INPUT/OUTPUT SPECIFICATIONS

VDD1 = VDDL = VDDC = VDDQ = VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, unless otherwise noted.

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CMOS INPUT/OUTPUT LEVELS

Input Voltage High

VIH

VDDIO × 0.65

Input Voltage Low

VIL

VDDIO × 0.35

Output Voltage High

VOH

SDIO/SDO

IOH = 3 mA

VDDIO × 0.7

AGCx

IOH = 0.5 mA

VDDIO × 0.7

Output Voltage Low

VOL

SDIO/SDO

IOL = 3 mA

0.4

AGCx

VOL

IOL = 0.5 mA

0.4

Input Capacitance

SPI TIMING

See Figure 148, Figure 149, and Figure 150

SCLK Frequency

fSCLK

MHz

SCLK Period

tSCLK

SCLK Pulse Width High

tHIGH

SCLK Pulse Width Low

tLOW

SDIO Setup Time

tDS

SDIO Hold Time

tDH

SPI_RESET Setup Time1

tSPI_RST

Not shown in Figure 148 to Figure 150

SCLK Falling Edge to SDO Valid

Propagation Delay

tACCESS

CSB Rising Edge to SDIO High-Z

CSB Fall to SCLK Rise Setup Time

SCLK Fall to CSB Rise Hold Time

1 This is the time required after a software or hardware reset until SPI access is available again.

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