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AD6676EBZ データシート(PDF) 85 Page - Analog Devices |
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AD6676EBZ データシート(HTML) 85 Page - Analog Devices |
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85 / 90 page  Data Sheet AD6676 Rev. D | Page 85 of 90 PHY Control 0 Register Address: 0x1EB, Reset: 0x1C, Name: SER1 Table 116. Bit Descriptions for SER1 Bits Bit Name Description Reset Access 7 SER_DRV_PS Serializer Polarity Selection. 0x0 RW 0 = Polarity not inverted. 1 = Polarity inverted. [6:0] RESERVED 0x1C RW PHY Control 1 Register Address: 0x1EC, Reset: 0x00, Name: SER2 Table 117. Bit Descriptions for SER1 Bits Bit Name Description Reset Access [7:4] SER_ITRIM Driver bias current trim with recommended setting of 0x0B. 0x9 RW [3:0] SER_RTRIM Resistor termination code with recommended setting of 0x0D. 0xB RW PHY Control 3 Register Address: 0x1EF, Reset: 0x00, Name: PRE-EMPHASIS Table 118. Bit Descriptions for PRE-EMPHASIS Bits Bit Name Description Reset Access 7 SER_EMP_PS1 Toggle Polarity of Lane 1 Emphasis. 0x0 RW [6:4] SER_EMP_IDAC1 Lane 1 IDAC Setting. 0x0 RW 00: 0 mV emphasis differential p-p. 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. 3 SER_EMP_PS0 Toggle polarity of Lane 0 emphasis. 0x0 RW [2:0] SER_EMP_IDAC0 Lane 0 IDAC Setting. 0x0 RW 00: 0 mV emphasis differential p-p. 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. ADC Standby 0 Register Address: 0x250, Reset: 0xFF, Name: STBY_DAC Table 119. Bit Descriptions for STBY_DAC Bits Bit Name Description Reset Access [7:0] STBY_DAC Setting register to 0x95 results in faster standby ADC recovery time. 0xFF RW |
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