DLPC3470 datasheet(16/70 Pages) TI1

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DLPC3470

DLPS110 – APRIL 2018

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(1)

It is recommended that VDDLP12 rail is tied to the VDD rail.

(2)

If the VDDLP12 is fed from a separate (from VDD) supply, the VDDLP12 power must sequence ON after the 1.1V core supply and must

sequence OFF before the 1.1V core supply.

(3)

These supplies have multiple valid ranges.

(4)

These I/O supply ranges are wider to facilitate additional filtering.

(5)

The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value at

0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with min and max estimated power

dissipation across process, voltage, and temperature. Thermal conditions vary by application, which will impact RθJA. Thus, maximum

operating ambient temperature varies by application.

(a) Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0 W × 30.3°C/W) = –30°C

(b) Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348 W × 30.3°C/W) = +94.4°C

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V(VDD)

Core power 1.1 V (main 1.1 V)

±5% tolerance

1.045

1.1

1.155

V(VDDLP12)

Reserved

±5% tolerance

See(1)(2)

1.045

1.10

1.155

V(VCC18)

All 1.8-V I/O power:

(1.8-V power supply for all I/O other than the host or

parallel interface and the SPI flash interface. This

includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1,

TSTPT, and JTAG pins.)

±8.5% tolerance

1.64

1.8

1.96

V(VCC_INTF)

Host or parallel interface I/O power: 1.8 to 3.3 V (includes

IIC0, PDATA, video syncs, and HOST_IRQ pins)

±8.5% tolerance

See (3)

1.64

1.8

1.96

2.28

2.5

2.72

3.02

3.3

3.58

V(VCC_FLSH)

Flash interface I/O power:1.8 to 3.3 V

±8.5% tolerance

See (3)

1.64

1.8

1.96

2.28

2.5

2.72

3.02

3.3

3.58

V(VDD_PLLM)

MCG PLL 1.1-V power

±9.1% tolerance

See (4)

1.025

1.1

1.155

V(VDD_PLLD)

DCG PLL 1.1-V power

±9.1% tolerance

See (4)

1.025

1.1

1.155

Operating ambient temperature(5)

–30

°C

Operating junction temperature

-30

105

°C

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC defined

standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC3470 controller PCB and thus the reported

thermal resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different , it is

the best information available during the design phase to estimate thermal performance.

(3)

Example: (0.5 W) × (0.2 °C/W)

≈ 1.00°C temperature rise.

6.4 Thermal Information

THERMAL METRIC(1)

DLPC3470 controller

UNIT

ZEZ (NFBGA)

201 PINS

RθJC

Junction-to-case thermal resistance

10.1

°C/W

RθJA

Junction-to-air thermal

resistance

at 0 m/s of forced airflow(2)

28.8

°C/W

at 1 m/s of forced airflow(2)

25.3

at 2 m/s of forced airflow(2)

24.4

ψJT

Temperature variance from junction to package top center temperature, per

unit power dissipation(3)

.23

°C/W

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