DLPC3470 datasheet(55/70 Pages) TI1

55 / 70 page

500 ms Min

PLL_REFCLK may be active

before power is applied.

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the controller is not ready for

operation, and then is driven low after

initialization is complete.

0 µs Min

0 µs

Max

PARKZ must be set low a

minimum of 32 µs before any

power is removed (except

VDDLP12), before PLL_REFCLK

is stopped and before RESETZ is

asserted low to allow time for the

DMD mirrors to be parked.

0 µs Min

5 ms Min

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and ASIC

oscillator cell dependent).

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ)

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

VDD_PLLM/D (1.1 V)

VDD (1.1 V)

VCC18 (1.8 V)

VDDLP12 (if not tied to VDD)

Point at which all supplies reach 95% of

their specified nominal values.

PARKZ must be set high a minimum

of 0 µs before RESETZ is released to

support auto-initialization.

PROJ_ON input

(GPIO_8)

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

I2C activity should cease

immediately upon active low

assertion of PARKZ.

0 µs

Min

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements defined

in the DLPA2000 specification.

32 µs Min

0 µs

Min

DLPC3470

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DLPS110 – APRIL 2018

Product Folder Links: DLPC3470

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System Power-Up and Power-Down Sequence (continued)

Figure 34. DLPC3470 controller Power-Up / PARKZ = 0 Initiated Fast PARK and Power-Down

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