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DLPC3470 データシート(PDF) 46 Page - Texas Instruments |
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DLPC3470 データシート(HTML) 46 Page - Texas Instruments |
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46 / 70 page  B C E D Video Video A A Pulse position changes on alternate subframes Both shutters off Next shutter on 46 DLPC3470 DLPS110 – APRIL 2018 www.ti.com Product Folder Links: DLPC3470 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated The period between DLPLink pulses alternates between the subframe period = D and the subframe period –D, where D is the delta period. Figure 28. 3D DLP Link Pulse Timing Table 8. 3D Link Nominal Timing Table HDMI Source Reference 3D DMD SEQUENCE RATE (Hz) A B C D E 23.6 94.5 25 500 628 128 >2000 24.0 96 25 500 628 128 >2000 49.0 98 25 500 628 128 >2000 50.0 100 25 500 628 128 >2000 51.0 102 25 500 628 128 >2000 59.0 118 25 500 628 128 >2000 60.0 120 25 500 628 128 >2000 61.0 122 25 500 628 128 >2000 8.3.2.9 DMD (Sub-LVDS) Interface The DLPC3470 controller ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. The DLPC3470 controller sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the DLPC3470 controller also supports a limited number of DMD interface swap configurations that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 8 shows the four options available for the DLP2010 (.2 WVGA) DMD specifically. Any unused DMD signal pairs should be left unconnected on the final board design. Table 9. DLP2010 (.2 WVGA) DMD – ASIC to 4-Lane DMD Pin Mapping Options DLPC3470 controller ASIC 4 LANE DMD ROUTING OPTIONS DMD PINS OPTION 1 Swap Control = x0 OPTION 2 Swap Control = x2 OPTION 3 Swap Control = x1 OPTION 4 Swap Control = x3 HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_H_P HS_WDATA_H_N HS_WDATA_A_P HS_WDATA_A_N Input DATA_p_0 Input DATA_n_0 HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_G_P HS_WDATA_G_N HS_WDATA_B_P HS_WDATA_B_N Input DATA_p_1 Input DATA_n_1 HS_WDATA_F_P HS_WDATA_F_N HS_WDATA_C_P HS_WDATA_C_N HS_WDATA_B_P HS_WDATA_B_N HS_WDATA_G_P HS_WDATA_G_N Input DATA_p_2 Input DATA_n_2 HS_WDATA_E_P HS_WDATA_E_N HS_WDATA_D_P HS_WDATA_D_N HS_WDATA_A_P HS_WDATA_A_N HS_WDATA_H_P HS_WDATA_H_N Input DATA_p_3 Input DATA_n_3 |
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