DLPC3470 datasheet(39/70 Pages) TI1

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DLPC3470

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DLPS110 – APRIL 2018

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8.3.2.2 Serial Flash Interface

DLPC3470 controller uses an external SPI serial flash memory device for configuration support. The minimum

required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while

the maximum supported is 16 Mb.

For access to flash, the DLPC3470 controller uses a single SPI interface operating at a programmable frequency

complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to

180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz.

Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz,

25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The DLPC3470 controller supports two independent SPI device selects; however, the flash must be connected to

SPI device select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to

device select zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then

transfers control to an auto-initialization routine within program memory. The DLPC3470 controller asserts the

HOST_IRQ output signal high while auto-initialization is in progress, then drives it low to signal its completion to

the host processor. Only after auto-initialization is complete will the DLPC3470 controller be ready to receive

commands through I2C.

The DLPC3470 controller should support any flash device that is compatible with the modes of operation,

features, and performance as defined in Table 4 and Table 5.

Table 4. SPI Flash Required Features or Modes of Operation

FEATURE

DLPC3470 CONTROLLER REQUIREMENT

SPI interface width

Single

SPI protocol

SPI mode 0

Fast READ addressing

Auto-incrementing

Programming mode

Page mode

Page size

256 B

Sector size

4 KB sector

Block size

any

Block protection bits

0 = Disabled

Status register bit(0)

Write in progress (WIP) {also called flash busy}

Status register bit(1)

Write enable latch (WEN)

Status register bits(6:2)

A value of 0 disables programming protection

Status register bit(7)

Status register write protect (SRWP)

Status register bits(15:8)

(that is expansion status byte)

The DLPC3470 controller only supports single-byte status register R/W command execution, and thus may

not be compatible with flash devices that contain an expansion status byte. However, as long as expansion

status byte is considered optional in the byte 3 position and any write protection control in this expansion

status byte defaults to unprotected, then the device should be compatible with DLPC3470 controller .

To support flash devices with program protection defaults of either enabled or disabled, the DLPC3470 controller

always assumes the device default is enabled and goes through the process of disabling protection as part of the

boot-up process. This process consists of:

•

A write enable (WREN) instruction executed to request write enable, followed by

•

A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable

latch (WEL) bit

•

After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes

0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC3470 controller issues:

•

A write enable (WREN) instruction to request write enable, followed by

•

A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

•

After the write enable latch (WEL) bit is set, the program or erase instruction is executed

•

Note the flash automatically clears the write enable status after each program and erase instruction

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