DLPC3470 datasheet(56/70 Pages) TI1

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DLPC3470

DLPS110 – APRIL 2018

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10.2 DLPC3470 controller Power-Up Initialization Sequence

It is assumed that an external power monitor will hold the DLPC3470 controller in system reset during power-up.

It must do this by driving RESETZ to a logic low state. It should continue to assert system reset until all ASIC

voltages have reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable.

During this time, most ASIC outputs will be driven to an inactive state and all bidirectional signals will be

configured as inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated.

These include LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full

signal descriptions in Pin Configuration and Functions. After power is stable and the PLL_REFCLK_I clock input

to the DLPC3470 controller is stable, then RESETZ should be deactivated (set to a logic high). The DLPC3470

controller then performs a power-up initialization routine that first locks its PLL followed by loading self

configuration data from the external flash. Upon release of RESETZ all DLPC3470 controller I/Os will become

active. Immediately following the release of RESETZ, the HOST_IRQ signal will be driven high to indicate that

the auto initialization routine is in progress. However, since a pullup resistor is connected to signal HOST_IRQ,

this signal will have already gone high before the DLPC3470 controller actively drives it high. Upon completion of

the auto-initialization routine, the DLPC3470 controller will drive HOST_IRQ low to indicate the initialization done

state of the DLPC3470 controller has been reached.

Note that the host processor can start sending I2C commands after HOST_IRQ goes low.

10.3 DMD Fast PARK Control (PARKZ)

The PARKZ signal is defined to be an early warning signal that should alert the ASIC 32 µs before DC supply

voltages have dropped below specifications in fast PARK operation. This allows the ASIC time to park the DMD,

ensuring the integrity of future operation. Note that the reference clock should continue to run and RESETZ

should remain deactivated for at least 32 µs after PARKZ has been deactivated (set to a logic low) to allow the

park operation to complete.

10.4 Hot Plug Usage

The DLPC3470 controller provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF).

This allows these inputs to be driven high even when no I/O power is applied. Under this condition, the

DLPC3470 controller will not load the input signal nor draw excessive current that could degrade ASIC reliability.

For example, the I2C bus from the host to other components would not be affected by powering off VCC_INTF to

the DLPC3470 controller . TI recommends weak pullups or pulldowns on signals feeding back to the host to

avoid floating inputs.

If the I/O supply (VCC_INTF) is powered off, but the core supply (VDD) is powered on, then the corresponding

input buffer may experience added leakage current, but this does not damage the DLPC3470 controller .

10.5 Maximum Signal Transition Time

Unless otherwise noted, 10 ns is the maximum recommended 20% to 80% rise or fall time to avoid input buffer

oscillation. This applies to all DLPC3470 controller input signals. However, the PARKZ input signal includes an

additional small digital filter that ignores any input buffer transitions caused by a slower rise or fall time for up to

150 ns.

DLPC3470 データシート(PDF) 56 Page - Texas Instruments

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