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AM652X データシート(PDF) 204 Page - Texas Instruments |
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AM652X データシート(HTML) 204 Page - Texas Instruments |
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204 / 299 page  MMC0 CLK _ MMC0 CMD _ MMC0 DAT[7:0] _ HS2005 HS2005 HS2006 HS2006 HS2001 HS2002H HS2002L SPRSP08_MMC0_07 MMC0 CLK _ MMC0 CMD _ MMC0 DAT[7:0] _ DDR1 DDR2 DDR2 DDR5 DDR5 DDR6 DDR6 DDR6 DDR6 DDR5 DDR5 DDR6 DDR6 SPRSP08_MMC0_06 204 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) P = output MMC0_CLK period in ns Figure 5-74. MMC0 SD Card Interface - JC64 High Speed DDR Transmitter Mode Table 5-70 presents Timing requirements and Switching characteristics for MMC0 - JEDS84 HS200 in receiver and transmitter mode (see Figure 5-75). Table 5-70. Switching Characteristics for MMC0 - JEDS84 HS200 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HS2001 fop(clk) Operating frequency, MMC0_CLK Positive-edge Reference Clock 192 MHz HS2002H tw(clkH) Pulse duration, MMC0_CLK high Positive-edge Reference Clock 0.5*P - 0.43 (1) ns HS2002L tw(clkL) Pulse duration, MMC0_CLK low Negative-edge Reference Clock 0.5*P - 0.43 (1) ns HS2005 td(clkL-cmdV) Delay time, MMC0_CLK falling clock edge to MMC0_CMD transition Negative-edge Reference Clock 1.33 3.28 ns HS2006 td(clkL-dV) Delay time, MMC0_CLK falling clock edge to MMC0_DAT[7:0] transition Positive-edge Reference Clock 1.33 3.28 ns (1) P = output MMC0_CLK period in ns Figure 5-75. MMC0 SD Card Interface - JEDS84 HS200 Transmitter Mode 5.11.5.16.2 MMC1—SD Card Interface MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card applications: • Default speed, SD Card, 4-bit data • High speed, SD Card, 4-bit data • UHS-I SDR12, SD Card, 4-bit data • UHS-I SDR25, SD Card, 4-bit data • UHS-I SDR50, SD Card, 4-bit data |
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