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AM652X データシート(PDF) 208 Page - Texas Instruments |
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AM652X データシート(HTML) 208 Page - Texas Instruments |
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208 / 299 page  MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR254 SDR258 SDR253 SDR257 SDR251 SDR252H SDR252L MMC1_07 SDR122 SDR121 SDR120 SDR123 SDR124 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] MMC1_06 208 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-81. MMC/SD in - High Speed SDR12 - Transmitter Mode 5.11.5.16.2.4 UHS-I SDR25, 4-bit data, half-cycle Table 5-77 and Table 5-78 present Timing requirements and Switching characteristics for MMC1 - SDR25 in receiver and transmitter mode (see Figure 5-82 and Figure 5-83). Table 5-77. Timing Requirements for MMC1 - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR253 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns SDR254 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns SDR257 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns SDR258 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns Table 5-78. Switching Characteristics for MMC1 - SD Card SDR25 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR251 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 48 MHz SDR252 H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns SDR252 L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns SDR255 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -7.5 3.5 ns SDR256 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -7.5 3.5 ns (1) P = output MMC1_CLK period in ns Figure 5-82. MMC/SD in - High Speed SDR25 - Receiver Mode |
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