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AM652X データシート(PDF) 205 Page - Texas Instruments |
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AM652X データシート(HTML) 205 Page - Texas Instruments |
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205 / 299 page  DSSD2 DSSD1 DSSD0 DSSD6 DSSD5 DSSD8 DSSD7 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] MMC1_01 205 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated • UHS-I SDR104, SD Card, 4-bit data • UHS-I DDR50, SD Card, 4-bit data NOTE For more information, see the Multimedia Card/Secure Digital (MMC/SD) Interface chapter of the Device TRM. 5.11.5.16.2.1 Default speed, 4-bit data, SDR, half-cycle Table 5-71 and Table 5-72 present Timing requirements and Switching characteristics for MMC1 - Default Speed in receiver and transmitter mode (see Figure 5-76 and Figure 5-77) Table 5-71. Timing Requirements for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DSSD5 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.44 ns DSSD6 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 0.17 ns DSSD7 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.44 ns DSSD8 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 0.17 ns Table 5-72. Switching Characteristics for MMC1 - SD Card Default Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DSSD0 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 24 MHz DSSD1 tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 19.49 ns DSSD2 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 19.49 ns DSSD3 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -14.39 14.39 ns DSSD4 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -14.39 14.39 ns (1) P = output MMC1_CLK period in ns Figure 5-76. MMC/SD in - Default Speed - Receiver Mode |
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