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AM652X データシート(PDF) 211 Page - Texas Instruments |
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AM652X データシート(HTML) 211 Page - Texas Instruments |
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211 / 299 page  MMC1 CLK _ MMC1 CMD _ MMC1 DAT _ [3:0] DDR500 DDR501 DDR502 DDR503(max) DDR503(min) DDR504(max) DDR504(min) DDR504(min) DDR504(max) MMC1_14 MMC1 CLK _ MMC1 CMD _ MMC1 DAT _ [3:0] DDR500 DDR501 DDR502 DDR505 DDR506 DDR508 DDR507 DDR507 DDR508 MMC1_13 211 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated 5.11.5.16.2.7 UHS-I DDR50, 4-bit data Table 5-82 and Table 5-83 present Timing requirements and Switching characteristics for MMC1 - DDR50 in receiver and transmitter mode (see Figure 5-88 and Figure 5-89). Table 5-82. Timing Requirements for MMC1 - SD Card DDR50 Mode NO. PARAME TER DESCRIPTION MODE MIN MAX UNIT DDR505 tsu(cmdV-clk) Setup time, MMC1_CMD valid before MMC1_CLK transition Positive-edge Reference Clock 6.21 ns DDR506 th(clk-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK transition Positive-edge Reference Clock 1.53 ns DDR507 tsu(dV-clk) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition Both-edge Reference Clock -0.45 ns DDR508 th(clk-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition Both-edge Reference Clock 1.67 ns Table 5-83. Switching Characteristics for MMC1 - SD Card DDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR500 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 48 MHz DDR501 tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns DDR502 tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns DDR503 td(clk-cmdV) Delay time, MMC1_CLK transition to MMC1_CMD transition Negative-edge Reference Clock 1.72 13.91 ns DDR504 td(clk-dV) Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition Both-edge Reference Clock 1.72 6.5 ns (1) P = output MMC1_CLK period in ns Figure 5-88. MMC/SD - High Speed SD - DDR - Data/Command Receive Figure 5-89. MMC/SD - High Speed SD - DDR - Data/Command Transmit |
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