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AM652X データシート(PDF) 209 Page - Texas Instruments |
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AM652X データシート(HTML) 209 Page - Texas Instruments |
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209 / 299 page  MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR504 SDR508 SDR503 SDR507 SDR501 SDR502H SDR502L MMC1_09 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] SDR251 SDR252L SDR252H HSSDR255 SDR256 SDR255 SDR256 MMC1_08 209 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-83. MMC/SD in - High Speed SDR25 - Transmitter Mode 5.11.5.16.2.5 UHS-I SDR50, 4-bit data, half-cycle Table 5-79 and Table 5-80 present Timing requirements and Switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 5-84 and Figure 5-85). Table 5-79. Timing Requirements for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR503 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock -0.69 ns SDR504 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns SDR507 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock -0.69 ns SDR508 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 1.67 ns ns Table 5-80. Switching Characteristics for MMC1 - SD Card SDR50 Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SDR501 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 96 MHz SDR502 H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 4.65 ns SDR502 L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 4.65 ns SDR505 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock 1.46 6.76 ns SDR506 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock 1.46 6.76 ns (1) P = output MMC1_CLK period in ns Figure 5-84. MMC/SD in - High Speed SDR50 - Receiver Mode |
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