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AM652X データシート(PDF) 230 Page - Texas Instruments |
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AM652X データシート(HTML) 230 Page - Texas Instruments |
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230 / 299 page  MII_RXCLK PMIR2 PMIR3 PMIR1 SPRS91x_TIMING_PRU_MII_RT_04 SPRS91x_TIMING_PRU_RGMII_RT_07 PRRG12 RGMII_TXC RGMII_TD[3:0] RGMII_TX_CTL PRRG13 230 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-115. PRU-ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG13 tt(TD) Transition time, TD 10 Mbps TBD ns 100 Mbps TBD ns 1000 Mbps 0.75 ns tt(TX_CTL) Transition time, TX_CTL 10 Mbps TBD ns 100 Mbps TBD ns 1000 Mbps 0.75 ns (1) P = Cycle time Figure 5-124. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Output Timing 5.11.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing NOTE In order to guarantee the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). Table 5-116. PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR1 tc(RX_CLK) Cycle time, RX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns PMIR2 tw(RX_CLKH) Pulse Duration, RX_CLK High 10 Mbps 140 260 ns 100 Mbps 14 26 ns PMIR3 tw(RX_CLKL) Pulse Duration, RX_CLK Low 10 Mbps 140 260 ns 100 Mbps 14 26 ns Figure 5-125. PRU_ICSSG MII_RXCLK Timing Table 5-117. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT1 tc(TX_CLK) Cycle time, TX_CLK 10 Mbps 399.96 400.04 ns 100 Mbps 39.996 40.004 ns |
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