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AM652X データシート(PDF) 234 Page - Texas Instruments |
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AM652X データシート(HTML) 234 Page - Texas Instruments |
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234 / 299 page  TRC_DATA TRC_CLK ( ) ( ) Worst Case 1 (Ideal) Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR9 DBTR5 DBTR7 DBTR8 DBTR8 DBTR9 SPRSP08_Debug_01 234 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated For more information, see section Universal Serial Bus (USB) Subsystem in chapter Peripherals of the device TRM. 5.11.6 Emulation and Debug 5.11.6.1 Debug Trace Table 5-124 and Figure 5-131 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-124. Debug Trace Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 10.16 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.33 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.33 ns DBTR4 tosu(TRC_DATAV- TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.27 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.27 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.27 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.27 ns DBTR8 trx(TRC_CLK_DATA_CTL) Output rise time, 30% VDD to 70% VDD 0.75 ns DBTR9 tfx(TRC_CLK_DATA_CTL) Output fall time, 70% VDD to 30% VDD 0.75 ns Figure 5-131. Debug Trace Timing 5.11.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG) For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-Access Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.11.6.2.1 JTAG Electrical Data and Timing Table 5-125, Table 5-126, and Figure 5-132 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-125. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 75 ns J2 tw(TCKH) Pulse width minimum, TCK high 30 ns J3 tw(TCKL) Pulse width minimum, TCK low 30 ns |
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