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AM652X データシート(PDF) 231 Page - Texas Instruments

部品番号 AM652X
部品情報  Sitara Processors
PDF  299 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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AM652X データシート(HTML) 231 Page - Texas Instruments

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MII_MRCLK (Input)
PMIR4
PMIR5
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
SPRS91x_TIMING_PRU_MII_RT_06
MII_TXCLK
PMIT2
PMIT3
PMIT1
PMIT4
PMIT4
SPRS91x_TIMING_PRU_MII_RT_05
231
AM6548, AM6528, AM6546
AM6526, AM6527
www.ti.com
SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Table 5-117. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
PMIT2
tw(TX_CLKH)
Pulse Duration, TX_CLK High
10 Mbps
140
260
ns
100 Mbps
14
26
ns
PMIT3
tw(TX_CLKL)
Pulse Duration, TX_CLK Low
10 Mbps
140
260
ns
100 Mbps
14
26
ns
PMIT4
tt(TX_CLK)
Transition time, TX_CLK
10 Mbps
5
ns
100 Mbps
5
ns
Figure 5-126. PRU_ICSSG MII_TXCLK Timing
Table 5-118. PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
PMIR4
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
10 Mbps
8
ns
tsu(RX_DV-RX_CLK)
Setup time, RX_DV valid before RX_CLK
8
ns
tsu(RX_ER-RX_CLK)
Setup time, RX_ER valid before RX_CLK
8
ns
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
100
Mbps
8
ns
tsu(RX_DV-RX_CLK)
Setup time, RX_DV valid before RX_CLK
8
ns
tsu(RX_ER-RX_CLK)
Setup time, RX_ER valid before RX_CLK
8
ns
PMIR5
th(RX_CLK-RXD)
Hold time, RXD[3:0] valid after RX_CLK
10 Mbps
8
ns
th(RX_CLK-RX_DV)
Hold time, RX_DV valid after RX_CLK
8
ns
th(RX_CLK-RX_ER)
Hold time, RX_ER valid after RX_CLK
8
ns
th(RX_CLK-RXD)
Hold time, RXD[3:0] valid after RX_CLK
100
Mbps
8
ns
th(RX_CLK-RX_DV)
Hold time, RX_DV valid after RX_CLK
8
ns
th(RX_CLK-RX_ER)
Hold time, RX_ER valid after RX_CLK
8
ns
Figure 5-127. PRU_ICSSG MII_RXD[3:0], MII_RXDV, and MII_RXER Timing



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