HT95C30P datasheet(6/42 Pages) HOLTEK

6 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Functional Description

Execution flow

The system clock for the telephone controller is derived

from a 32768Hz crystal oscillator. A built-in frequency up

conversion circuit provides dual system clock, namely;

32768Hz and 3.58MHz. The system clock is internally

divided into four non-overlapping clocks. One instruc-

tion cycle consists of four system clock cycles. Instruc-

tion fetching and execution are pipelined in such a way

that a fetch takes an instruction cycle while decoding

and execution takes the next instruction cycle. The

pipelining scheme causes each instruction to be effec-

tively executed in a instruction cycle. If an instruction

changes the program counter, two instruction cycles are

required to complete the instruction.

Program counter

- PC

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory. After accessing a program memory word

to fetch an instruction code, the contents of the program

counter are incremented by 1. The program counter

then points to the memory word containing the next in-

struction code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

subroutine, the program counter manipulates the pro-

gram transfer by loading the address corresponding to

each instruction. The conditional skip is activated by in-

structions. Once the condition is met, the next instruc-

tion, fetched during the current instruction execution, is

discarded and a dummy cycle replaces it to get the

proper instruction. Otherwise proceed to the next in-

struction.

The program counter lower order byte register

(PCL:06H) is a readable and write-able register. Moving

data into the PCL performs a short jump. The destina-

tion will be within 256 locations. When a control transfer

takes place, an additional dummy cycle is required.

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

. e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

. e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

. e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

P C

Execution flow

Mode

Program Counter

*11

*10

Initial reset

000000000000

External interrupt

000000000100

Timer/Event Counter 0 overflow

000000001000

Timer/Event Counter 1 overflow

000000001100

RTC interrupt

000000010100

Dialer I/O interrupt

000000011000

Skip

Program Counter+2

Loading PCL

*11

*10

Jump, call branch

#11

#10

Return from subroutine

S11

S10

Note: *11~*0: Program counter bits

S11~S0: Stack register bits

#11~#0: Instruction code bits

@7~@0: PCL bits

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