HT95C30P datasheet(11/42 Pages) HOLTEK

11 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Bits

Label

R/W

Function

INTC0

(0BH)

EMI

Controls the master (global) interrupt (1=enabled; 0=disabled)

EEI

Controls the external interrupt (1=enabled; 0=disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

ET1I

Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

EIF

External interrupt request flag (1=active; 0=inactive)

T0F

Timer/Event Counter 0 request flag (1=active; 0=inactive)

T1F

Timer/Event Counter 1 request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC1

(1EH)

Unused bit, read as

²0²

ERTCI

Control the real time clock interrupt (1=enable; 0=disable)

EDRI

Control the dialer I/O interrupt (1=enable; 0=disable)

Unused bit, read as

²0²

Unused bit, read as

²0²

RTCF

Internal real time clock interrupt request flag (1=active; 0=inactive)

DRF

Internal dialer I/O interrupt request flag (1=active: 0=inactive)

Unused bit, read as

²0²

The Timer/Event Counter 1 interrupt is generated by a

timeout overflow and the interrupt request flag T1F will

be set. When the Timer/Event Counter 1 interrupt is en-

abled, the stack is not full and the T1F bit is set, a sub-

routine call to location 0CH will occur. The interrupt

request flag T1F and EMI bits will be cleared to disable

further interrupts.

The real time clock interrupt is generated by a 1Hz RTC

generator. When the RTC time-out occurs, the interrupt

request flag RTCF will be set. When the RTC interrupt is

enabled, the stack is not full and the RTCF is set, a sub-

routine call to location 14H will occur. The interrupt re-

quest flag RTCF and EMI bits will be cleared to disable

other interrupts.

The dialer I/O interrupt is triggered by any edge transi-

tion onto HKS pin or a falling edge transition onto HDI

pin or a rising edge transition onto HFI pin, the interrupt

request flag DRF will be set. When the dialer I/O inter-

rupt is enabled, the stack is not full and the DRF is set, a

subroutine call to location 18H will occur. The interrupt

request flag DRF and EMI bits will be cleared to disable

other interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine,

²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an

interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt

04H

Timer/Event Counter 0 interrupt

08H

Timer/Event Counter 1 interrupt

0CH

Real time clock interrupt

14H

Dialer I/O interrupt

18H

Priority of the interrupt

EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to con-

trol the enabling/disabling of interrupts. These bits pre-

vent the requested interrupt from being serviced. Once

the interrupt request flags (EIF, T0F, T1F, RTCF, DRF)

are set by hardware or software, they will remain in the

INTC0 or INTC1 registers until the interrupts are ser-

viced or cleared by a software instruction.

It is recommended that a program should not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and enabling the interrupt is not well

controlled, the original control sequence will be dam-

aged once the

²CALL² operates in the interrupt subrou-

tine.

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