HT95C30P datasheet(17/42 Pages) HOLTEK

17 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Timer/Event Counter 0 and is defined by TMR1C. The

timer/event counter control registers define the operat-

ing mode, counting enable or disable and active edge.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR0 or INT/TMR1) pin. The timer mode functions as

a normal timer with the clock source coming from in-

struction clock (TMR0) or 32768Hz (TMR1). The pulse

width measurement mode can be used to count the high

or low level duration of the external signal (TMR0 or

INT/TMR1). The counting is based on the 32768Hz

clock for TMR1 or instruction clock for TMR0.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. If an over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the correspond-

ing interrupt request flag (T0F/T1F) at the same time.

In pulse width measurement mode with the TON and TE

bits equal to 1, once the TMR0/TMR1 pin has received a

transient from low to high (or high to low; if the TE bit is

0) it will start counting until the TMR0/TMR1 pin returns

to the original level and resets the TON. The measured

result will remain in the timer/event counter even if the

activated transient occurs again. In other words, only 1

cycle measurement can be done. Until setting the TON,

the cycle measurement will function again as long as it

receives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and continue to measure the width and issues the inter-

rupt request just like the other two modes.

To enable the counting operation, the timer on bit (TON)

should be set to 1. In the pulse width measurement

mode, the TON will be cleared automatically after the

measurement cycle is completed. But in the other two

modes the TON can only be reset by instruction. The

overflow of the timer/event counter is one of the

wake-up sources. No matter what the operation mode

is, writinga0to ET0I/ET1I can disable the correspond-

ing interrupt service.

In the case of timer/event counter off condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turned on, data written to the

timer/event counter is reserved only in the timer/event

counter preload register. The timer/event counter will go

on operating until an overflow occurs.

Input/output ports

There are 20 bidirectional input/output lines in the tele-

phone controller, labeled as PA, PB and PE. All of these

I/O ports can be used for input and output operations.

For input operation, these ports are non-latching, that is,

the inputs must be ready at the T2 rising edge of instruc-

tion

²MOV A,[m]² (m=12H, 14H or 1AH). For output op-

eration, all the data is latched and remains unchanged

until the output latch is rewritten.

Each I/O line has its own control register (PAC,PBC,

PEC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

can be reconfigured dynamically under software control.

To make one I/O line to function as an input line, the cor-

responding latch of the control register must be written

with a

²1². The pull-high resistance shows itself auto-

matically if the pull-high option is selected. The input

source also depends on the control register. If the con-

trol register bit is

²1², the input will read the pad state. If

the control register bit is

²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS is the only configuration. Each bit of these in-

put/output latches can be set or cleared by

²SET [m].i²

and

²CLR [m].i² (m=12H, 14H or 1AH) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. They are selected by mask option per bit.

There is a pull-high option available for all I/O lines.

Once the pull-high option of an I/O line is selected, the

I/O lines have pull-high resistor. Otherwise, the pull-high

resistor is absent. It should be noted that a non-pull-high

I/O line operating in input mode may cause a floating

state.

I/O port pull-high, wake-up function are selected by

mask option

I/O

Port

Output

Input

Pull-high

Resistor

Wake-up

Function

CMOS

Selected per bit

Selected

per bit

CMOS

Selected per bit

CMOS

Selected per nibble

Note: X: unavailable

The PE0~PE3 and SEG16~SEG19 share the same

pads. They can be selected per nibble by software op-

tion at any time.

When the PE0~PE3 are not selected, the I/O port con-

trol register, PEC (1BH) could be read/write-able and be

used as a general user RAM, but this function is not

available for register PE (1AH).

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