HT95C30P datasheet(10/42 Pages) HOLTEK

10 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU not only saves the results of a data operation

but also changes the status register.

Status register

- STATUS

This status register contains the carry flag (C), auxiliary

carry flag (AC), zero flag (Z), overflow flag (OV), power

down flag (PD), and watchdog time-out flag (TO). It also

records the status information and controls the opera-

tion sequence.

Except for the TO and PD flags, bits in the status regis-

ter can be altered by instructions, similar to the other

registers. Data written into the status register will not

change the TO or PD flag. Operations related to the sta-

tus register may yield different results from those in-

tended. The TO flag can be affected only by system

power-up, a WDT time-out or executing the

²CLR WDT²

²HALT² instruction. The PD flag can be affected only

by executing the

²HALT² or ²CLR WDT² instruction or

during a system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack.

If the contents of the status are important and if the sub-

routine can corrupt the status register, precautions must

be taken to save it .

Interrupt

The telephone controller provides an external interrupt,

internal timer/event counter interrupt, an internal real

time clock interrupt and internal dialer I/O interrupt. The

Interrupt Control Registers 0 and Interrupt Control Reg-

ister 1 both contains the interrupt control bits that set the

enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by hardware clearing the EMI

bit). This scheme may prevent any further interrupt nest-

ing. Other interrupt requests may occur during this inter-

val but only the interrupt request flag is recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 (INTC1) may be set to allow interrupt nesting.

If the stack is full, any other interrupt request will not be

acknowledged, even if the related interrupt is enabled,

until the stack pointer is decremented. If immediate ser-

vice is desired, the stack must be prevented from be-

coming full.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

External interrupt is triggered by a high to low transition

of the INT/TMR1 pin and the interrupt request flag EIF

will be set. When the external interrupt is enabled, the

stack is not full and the external interrupt is active, a sub-

routine call to location 04H will occur. The interrupt re-

quest flag EIF and EMI bits will be cleared to disable

other interrupts.

The Timer/Event Counter 0 interrupt is generated by a

timeout overflow and the interrupt request flag T0F will

be set. When the Timer/Event Counter 0 interrupt is en-

abled, the stack is not full and the T0F bit is set, a sub-

routine call to location 08H will occur. The interrupt

request flag T0F and EMI bits will be cleared to disable

further interrupts.

Label

Bits

Function

STATUS

(0AH)

C is set if the operation results in a carry during an addition operation or if a borrow

does not take place during a subtraction operation; otherwise C is cleared. Also it is

affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no bor-

row from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry

out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT instruction.

PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction.

TO is set by a WDT time-out.

6, 7

Unused bit, read as

²0²

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