HT95C30P datasheet(14/42 Pages) HOLTEK

14 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Once a Sleep mode or Idle mode wake-up event occurs,

it will take SST delay time (1024 system clock period) to

resume to Green mode. In other words, a dummy period

is inserted after a wake-up. If the wake-up results from

an interrupt acknowledge signal, the actual interrupt

subroutine execution will be delayed by one or more cy-

cles. If the wake-up results in the next instruction execu-

tion, this will be executed immediately after the dummy

period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the Sleep mode

or Idle mode.

The Sleep mode or Idle mode is initialized by the HALT

instruction and results in the following.

· The system clock will be turned off.

· The WDT function will be disabled if the WDT clock

source is the instruction clock.

· The WDT function will be disabled if the WDT clock

source is the 32768Hz in Idle mode.

· The WDT will still function if the WDT clock source is

the WDT OSC.

· If the WDT function is still enabled, the WDT counter

and WDT prescaler will be cleared and recounted

again.

· The contents of the on chip RAM and registers remain

unchanged.

· All the I/O ports maintain their original status.

· The flag PD is set and the flag TO is cleared by hard-

ware.

Reset

There are three ways in which a reset can occur.

· Power on reset.

· A low pulse onto RES pin.

· WDT time-out.

After these reset conditions, the Program Counter and

Stack Pointer will be cleared to 0.

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem is reset or awakes from the Sleep or Idle operation

mode.

By examining the processor status flags PD and TO, the

software program can distinguish between the different

²chip resets².

Reset Condition

Power on reset

External reset during Normal mode or

Green mode

External reset during Sleep mode or

Idle mode

WDT time-out during Normal mode or

Green mode

WDT time-out during Sleep mode or

Idle mode

Note:

²u² means ²unchanged²

The functional units chip reset status are shown below:

Program Counter

000H

Interrupt

Disabled

Prescaler

Cleared

WDT

Cleared

After a master reset, WDT

begins counting.

(If WDT function is enabled

by mask option)

Timer/Event Counter 0/1 Off

Input/output Port

Input mode

Stack Pointer

Points to the top of the stack

V D D

R E S

1 0 0 k W

0 . 1 m .

Reset circuit

W a r m R e s e t

W D T

C o l d R e s e t

H A L T

S Y S C L K

S S T

1 0 - b i t R i p p l e

C o u n t e r

W D T t i m e - o u t

E x t e r n a l R E S

S y s t e m R e s e t

Reset configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset timing chart

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