24LC256

256K I

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7

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle,

this can be used to determine when the cycle is complete (this

feature can be used to maximize bus throughput.) Once the

stop condition for a write command has been issued from the

master, the device initiates the internally timed write cycle.

ACK polling can be initiated immediately. This involves the

master sending a start condition, followed by the control byte

for a write command(

=0). If the device is still busy with

the write cycle, then no ACK will be returned. If no ACK if

returned, then the start bit and control byte must be resent. If

the cycle is complete, then the device , See Figure 7-1 for flow

diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING FLOW

8.0 READ OPERATION

Read operations are initiated in the same way as write operations with the exception that the

bit of the control byte is set to

one. There are three basic types of read operations: current address read, random read, and sequential read.

8.1 Current Address Read

The 24xx256 contains an address counter that maintains the address of the last word accessed, internally incremented by one.

Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would

access data from address n+1.

Upon receipt of the control byte with

bit set to one, the 24xx256 issues an acknowledge and transmits the 8-bit data word.

The master will not acknowledge the transfer but does generate a stop condition and the 24xx256 discontinues transmission

(Figure 8-1)

FIGURE 8-1: CURRENT ADDRESS READ