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AM652X データシート(PDF) 217 Page - Texas Instruments |
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AM652X データシート(HTML) 217 Page - Texas Instruments |
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217 / 277 page  217 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated 5.9.5.18 OSPI For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.5.18.1 OSPI with Data Training Table 5-83. OSPI Switching Characteristics - Data Training PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6.02 ns DDR, 3.3V 7.52 ns tc(CLK) Cycle time, CLK SDR, 1.8V 6.02 ns SDR, 3.3V 7.52 ns 5.9.5.18.2 OSPI without Data Training NOTE The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 5-88 found in this section. Table 5-84, Table 5-85, Figure 5-84, and Figure 5-85 present switching characteristics for OSPI DDR and SDR Mode. Table 5-84. OSPI Switching Characteristics - DDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low -0.3+0.475×P (2) ns O3 tw(CLKH) Pulse duration, CLK high -0.3+0.475×P (2) ns O4 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7-0.475 × P – 0.975 × N × R (3) (4) (5) 0-0.475 × P – 0.975 × N × R (3) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -8-0.475 × P – 0.975 × N × R (3) (4) (5) 0-0.475 × P – 0.975 × N × R (3) (4) (5) ns O5 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7+0.475 × P + 0.975 × N × R (3) (4) (5) 0+0.475 × P + 0.975 × N × R (3) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -8+0.475 × P + 0.975 × N × R (3) (4) (5) 0+0.475 × P + 0.975 × N × R (3) (4) (5) ns O6 td(CLK-D) Delay time, CLK active edge to D[i:0] transition 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.7 -1.56 ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -7.7 -1.56 ns |
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