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AM652X データシート(PDF) 220 Page - Texas Instruments |
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AM652X データシート(HTML) 220 Page - Texas Instruments |
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220 / 277 page  OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 OSPI_DQS OSPI_D[i:0] O16 O15 OSPI_TIMING_04 OSPI_CLK OSPI_D[i:0] O14 O13 OSPI_TIMING_03 220 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate. Figure 5-86. OSPI Timing Requirements - DDR, No Loopback Clock and Internal Pad Loopback Clock Figure 5-87. OSPI Timing Requirements - DDR, External Loopback Clock and DQS Table 5-87. OSPI Timing Requirements - SDR Mode (1) NO. PARAMET ER DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge 1.8V, No Loopback Clock -2.18 ns 3.3V, No Loopback Clock -1.7 ns O20 th(CLK-D) Hold time, D[i:0] valid after active CLK edge 1.8V, No Loopback Clock 7.62 ns 3.3V, No Loopback Clock 8.1 ns O21 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK input (DQS) edge 1.8V, External Board Loopback Clock -3.24 ns 3.3V, External Board Loopback Clock -2.72 ns O22 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK input (DQS) edge 1.8V, External Board Loopback Clock 3.81 ns 3.3V, External Board Loopback Clock 4.33 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 Figure 5-88. OSPI Timing Requirements - SDR, No Loopback Clock and Internal Pad Loopback Clock |
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