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AM652X データシート(PDF) 219 Page - Texas Instruments |
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AM652X データシート(HTML) 219 Page - Texas Instruments |
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219 / 277 page  OSPI_CLK OSPI_D[i:0] OSPI_TIMING_02 OSPI_CSn O10 O11 O9 O8 O12 O7 219 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Figure 5-85. OSPI Switching Characteristics - SDR Table 5-86, Table 5-87, Figure 5-86, Figure 5-87, Figure 5-88, and Figure 5-89 presents timing requirements for OSPI DDR and SDR Mode. Table 5-86. OSPI Timing Requirements - DDR Mode (1) NO. PARAMETE R DESCRIPTION MODE MIN MAX UNIT O13 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge 1.8V, No Loopback Clock; 1.8V, Internal Pad Loopback Clock 5.23 ns 3.3V, No Loopback Clock; 3.3V, Internal Pad Loopback Clock 6.19 ns O14 th(CLK-D) Hold time, D[i:0] valid after active CLK edge 1.8V, No Loopback Clock; 1.8V, Internal Pad Loopback Clock 1.84 ns 3.3V, No Loopback Clock; 3.3V, Internal Pad Loopback Clock 2.34 ns O15 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK (DQS) edge 1.8V, External Board Loopback Clock 0.52 ns 3.3V, External Board Loopback Clock 1.97 ns O16 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK (DQS) edge 1.8V, External Board Loopback Clock 1.8 (2) ns 3.3V, External Board Loopback Clock 2.2 (2) ns O17 tsu(D-DQS) Setup time, DQS edge to D[i:0] transition 1.8V, OSPI0 DQS; 1.8V, OSPI1 DQS -0.46 ns 3.3V, OSPI0 DQS; 3.3V, OSPI1 DQS -0.66 ns O18 th(DQS-D) Hold time, DQS edge to D[i:0] transition 1.8V, OSPI0 DQS; 1.8V, OSPI1 DQS 3.59 ns 3.3V, OSPI0 DQS; 3.3V, OSPI1 DQS 7.92 ns |
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