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AM652X データシート(PDF) 221 Page - Texas Instruments |
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AM652X データシート(HTML) 221 Page - Texas Instruments |
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221 / 277 page  OSPI_DQS OSPI_D[i:0] OSPI_TIMING_06 O21 O 2 2 221 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Figure 5-89. OSPI Timing Requirements - SDR, External Loopback Clock Table 5-88. OSPI DLL Delay Mapping for Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BITFIELD DELAY VALUE 1.8V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x45 1.8V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x4B 3.3V, OSPI0 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x46 3.3V, OSPI1 DDR TX PHY_CONFIG_TX_DLL_DELAY_FLD 0x4C 1.8V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x14 1.8V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x16 3.3V, OSPI0 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3A 3.3V, OSPI1 DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3E All other modes PHY_CONFIG_TX_DLL_DELAY_FLD, PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM. 5.9.5.19 OLDI Table 5-89. OLDI Switching Characteristics NO. PARAME TER DESCRIPTION(1) MIN TYP MAX UNIT OLDI1 tt(LHTT) Low-to-high transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0 (Fast rise/fall disabled) 0.5 ns Low-to-high transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1 (Fast rise/fall enabled) 0.25 ns OLDI2 tt(HLTT) High-to-low transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0 (Fast rise/fall disabled) 0.5 ns High-to-low transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1 (Fast rise/fall enabled) 0.25 ns OLDI3 tc(CLK) Output pixel clock period (OLDI0_CLKP/N) 6.06 110.01 ns OLDI4 tw(BIT) Output bit width (OLDI0_AxP/N, x = [3:0]) 1 UI(2) OLDI5 t(TPPx, x=[6:0]) Output pulse positions normalized for each bit (OLDI0_AxP/N, x = [3:0]) 7-1 UI(2) OLDI6 Δt(TPP) Variation of pulse positions for each bit from their normalized center (OLDI0_AxP/N, x = [3:0]) 0.1 UI(2) OLDI7 tsk(TCCS) Output channel to channel skew (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0]) 50 ps OLDI8 tj(TJCC) Output jitter cycle-to-cycle (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0]) 0.04 UI(2) OLDI9 tj(IJIT) Total jitter tolerance (Includes data to clock skew, pulse position variation from normalized edges (OLDI0_AxP/N, x = [3:0]) 0.25 UI(2) |
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