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AM652X データシート(PDF) 218 Page - Texas Instruments |
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AM652X データシート(HTML) 218 Page - Texas Instruments |
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218 / 277 page  OSPI_CLK OSPI_D[i:0] OSPI_TIMING_01 OSPI_CSn O6 O6 O4 O3 O2 O1 O5 218 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time (3) P = SCLK period (4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (5) R = refclk Figure 5-84. OSPI Switching Characteristics - DDR Table 5-85. OSPI Switching Characteristics - SDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, CLK 1.8V 7 ns 3.3V 7.52 ns O8 tw(CLKL) Pulse duration, CLK low -0.3+0.475×P (2) ns O9 tw(CLKH) Pulse duration, CLK high -0.3+0.475×P (2) ns O10 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V -1-0.475 × P – 0.975 × N × R (3) (4) (5) 1-0.475 × P – 0.975 × N × R (3) (4) (5) ns 3.3V -1-0.475 × P – 0.975 × N × R (3) (4) (5) 1-0.475 × P – 0.975 × N × R (3) (4) (5) ns O11 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V -1+0.475 × P + 0.975 × N × R (3) (4) (5) 1+0.475 × P + 0.975 × N × R (3) (4) (5) ns 3.3V -1+0.475 × P + 0.975 × N × R (3) (4) (5) 1+0.475 × P + 0.975 × N × R (3) (4) (5) ns O12 td(CLK-D) Delay time, CLK active edge to D[i:0] transition 1.8V -1.15 1.25 ns 3.3V -1.33 1.51 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time (3) P = SCLK period (4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (5) R = refclk |
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