STM8S datasheet(444/467 Pages) STMICROELECTRONICS

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Analog/digital converter (ADC)

RM0016

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DocID14587 Rev 14

24.11.4

ADC configuration register 1 (ADC_CR1)

Address offset: 0x21

Reset value: 0x00

654

3210

Reserved

SPSEL[2:0]

Reserved

CONT

ADON

Bit 7 Reserved, always read as 0.

Bits 6:4 SPSEL[2:0]: Prescaler selection

These control bits are written by software to select the prescaler division factor.

000: fADC = fMASTER/2

001: fADC = fMASTER/3

010: fADC = fMASTER/4

011: fADC = fMASTER/6

100: fADC = fMASTER/8

101: fADC = fMASTER/10

110: fADC = fMASTER/12

111: fADC = fMASTER/18

See Section 24.5.2 on page 431.

Note: It is recommended to change the SPSEL bits when ADC is in power down. This is because

internally there can be a glitch in the clock during this change. Otherwise the user is required to

ignore the 1st converted result if the change is done when ADC is not in power down.

Bits 3:2 Reserved, always read as 0.

Bit 1 CONT: Continuous conversion

This bit is set and cleared by software. If set, conversion takes place continuously till this bit is reset

by software.

0: Single conversion mode

1: Continuous conversion mode

Bit 0 ADON: A/D Converter on/off

This bit is set and reset by software. This bit must be written to wake up the ADC from power down

mode and to trigger the start of conversion. If this bit holds a value of 0 and a 1 is written to it then it

wakes the ADC from power down mode. Conversion starts when this bit holds a value of 1 and a 1 is

written to it. As soon as the ADC is powered on, the output stage of the selected channel is disabled.

0: Disable ADC conversion/calibration and go to power down mode.

1: Enable ADC and to start conversion

Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is

not triggered. This is to prevent triggering an erroneous conversion.

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