STM8S datasheet(66/467 Pages) STMICROELECTRONICS

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Interrupt controller (ITC)

RM0016

66/467

DocID14587 Rev 14

Figure 16. Nested interrupt management

6.6

External interrupts

Five interrupt vectors are dedicated to external Interrupt events:

•

5 lines on Port A: PA[6:2]

•

8 lines on Port B: PB[7:0]

•

8 lines on Port C: PC[7:0]

•

7 lines on Port D: PD[6:0]

•

8 lines on Port E: PE[7:0]

PD7 is the Top Level Interrupt source (TLI), except for 20-pin packages on which the Top

Level Interrupt source (TLI) can be available on the PC3 pin using an alternate function

remapping option bit. Refer to option bytes section in the product datasheet for more details.

To generate an interrupt, the corresponding GPIO port must be configured in input mode

with interrupts enabled. Refer to the register description in the GPIO chapter for details.

The interrupt sensitivity must be configured in the external interrupt control register 1

(EXTI_CR1) and external interrupt control register 2 (EXTI_CR2) (see Section 6.9.3 and

Section 6.9.4.).

6.7

Interrupt instructions

Table 11 shows the interrupt instructions.

MSv47718V2

Software

priority level

3/0

11/10

RIM

TRAP

IT3

IT1

Main

IT2

IT4

IT1

Main

IT0

Table 11. Dedicated interrupt instruction set

Instruction

New description

Function/example

HALT

Entering Halt mode

IRET

Interrupt routine return

Pop CCR, A, X, Y, PC

JRM

Jump if I1:0=11 (level 3)

I1:0=11 ?

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