STM8S datasheet(129/467 Pages) STMICROELECTRONICS

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RM0016

Window watchdog (WWDG)

133

Figure 28. Watchdog block diagram

The application program must write in the WWDG_CR register at regular intervals during

normal operation to prevent an MCU reset. This operation must occur only when the counter

value is lower than the window register value. The value to be stored in the WWDG_CR

•

Enabling the watchdog:

When software watchdog is selected (by option byte), the watchdog is disabled after a

reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot

be disabled again except by a reset.

When hardware watchdog is selected (by option byte), the watchdog is always active

and the WDGA bit is not used.

•

Controlling the downcounter:

This downcounter is free-running: It counts down even if the watchdog is disabled.

When the watchdog is enabled, the T6 bit must be set to prevent generating an

immediate reset.

The T[5:0] bits contain the number of increments which represents the time delay

before the watchdog produces a reset (see Figure 29: Approximate timeout duration).

The timing varies between a minimum and a maximum value due to the unknown

status of the prescaler when writing to the WWDG_CR register (see Figure 30).

The window register (WWDG_WR) contains the high limit of the window: To prevent a

reset, the downcounter must be reloaded when its value is lower than the window

process.

Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

•

Watchdog reset on halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the

HALT instruction will generate a reset.

MSv45272V1

RESET

Comparator = 1 when

T6:0 > W6:0

CMP

Write WWDG_CR

W6 W5 W4 W3 W2 W1 W0

WATCHDOG WINDOW REGISTER (WWDG_WR)

WDGA

WATCHDOG CONTROL REGISTER (wWDG_CR)

7-BIT DOWNCOUNTER (CNT)

WDG PRESCALER

DIV12288

fCPU

(from clock)

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