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STM8S データシート(PDF) 307 Page - STMicroelectronics |
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STM8S データシート(HTML) 307 Page - STMicroelectronics |
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307 / 467 page  DocID14587 Rev 14 307/467 RM0016 Inter-integrated circuit (I2C) interface 319 Note: When STOP or START is set, the user must not perform any write access to I2C_CR2 before the control bit is cleared by hardware. Otherwise, a second STOP or START request may occur. 21.7.3 Frequency register (I2C_FREQR) Address offset: 0x02 Reset value: 0x00 7 654 3210 Reserved FREQ[5:0] r rw Bits 7:6 Reserved Bits 5:0 FREQ[5:0] Peripheral clock frequency. (1) The FREQ field is used by the peripheral to generate data setup and hold times compliant with the I2C specifications. The FREQ bits must be programmed with the peripheral input clock frequency value: The allowed range is between 1 MHz and 24 MHz 000000: not allowed 000001: 1 MHz 000010: 2 MHz ... 011000: 24 MHz Higher values: not allowed 1. The minimum peripheral clock frequencies for respecting the I2C bus timings are: 1 MHz for standard mode and 4 MHz for fast mode |
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