STM8S datasheet(316/467 Pages) STMICROELECTRONICS

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Inter-integrated circuit (I2C) interface

RM0016

316/467

DocID14587 Rev 14

21.7.12

Clock control register high (I2C_CCRH)

Address offset: 0x0C

Reset value: 0x00

Note:

The CCR registers must be configured only when the I²C is disabled (PE=0).

fMASTER = multiple of 10 MHz is required to generate Fast clock at 400 kHz. fMASTER ≥ 1

MHz is required to generate Standard clock at 100 kHz.

654

3210

F/S

DUTY

Reserved

CCR[11:8]

Bit 7 F/S: I2C master mode selection

0: Standard mode I2C

1: Fast mode I2C

Bit 6 DUTY: Fast mode duty cycle

0: Fast mode tlow/thigh = 2

1: Fast mode tlow/thigh = 16/9 (see CCR)

Bits 5:4 Reserved

Bits 3:0 CCR[11:8]: Clock control register in Fast/Standard mode (Master mode)

Controls the SCLH clock in master mode.

– Standard mode:

Period(I2C) = 2 * CCR * tMASTER

thigh = CCR * tMASTER

tlow = CCR * tMASTER

– Fast mode:

If DUTY = 0:

Period(I2C) = 3 * CCR * tMASTER

thigh = CCR * tMASTER

tlow = 2 * CCR * tMASTER

If DUTY = 1: (to reach 400 kHz)

Period(I2C) = 25 * CCR * tMASTER

thigh = 9 * CCR * tMASTER

tlow = 16 * CCR * tMASTER

For instance: in standard mode, to generate a 100 kHz SCL frequency:

If FREQR = 08, tMASTER = 125 ns so CCR must be programmed with 0x28

(0x28 <=> 40 x 125 ns = 5000 ns.)

Note: thigh = tr(SCL) + tw(SCLH). See device datasheet for the definitions of parameters

tlow = tf(SCL) + tw(SCLL). See device datasheet for the definitions of parameters

The real frequency may differ due to the analog noise filter input delay.

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