STM8S datasheet(381/467 Pages) STMICROELECTRONICS

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RM0016

Controller area network (beCAN)

427

Figure 142. beCAN operating modes

23.4

Operating modes

beCAN has three main operating modes: Initialization, Normal and Sleep. After a

hardware reset, beCAN is in sleep mode to reduce power consumption. The software

requests beCAN to enter Initialization or Sleep mode by setting the INRQ or SLEEP bits in

the CAN_MCR register. Once the mode has been entered, beCAN confirms it by setting the

INAK or SLAK bits in the CAN_MSR register. When neither INAK nor SLAK are set, beCAN

is in Normal mode. Before entering Normal mode beCAN always has to synchronize on

the CAN bus. To synchronize, beCAN waits until the CAN bus is idle, this means 11

consecutive recessive bits have been monitored on CANRX.

Note:

The beCAN controls the PG0 port (CAN_TX pin) when the beCAN is in Normal mode,

whereas the PG0 port is controlled by the PG_ODR and PG_DDR GPIO registers while the

beCAN is in Initialization mode or in Sleep mode. Therefore the PG_ODR and PG_DDR

registers must be configured in order to maintain a recessive state on CAN_TX pin.

23.4.1

Initialization mode

The software initialization can be done while the hardware is in Initialization mode. To enter

this mode the software sets the INRQ bit in the CAN_MCR register and waits until the

hardware has confirmed the request by setting the INAK bit in the CAN_MSR register.

To leave Initialization mode, the software clears the INQR bit. beCAN has exit Initialization

mode once the INAK bit has been cleared by hardware. However the Rx line has to be in

recessive state to leave this mode.

While in Initialization mode, all message transfers to and from the CAN bus are stopped and

the status of the CAN bus output CANTX is recessive (high).

Entering Initialization Mode does not change any of the configuration registers.

To initialize the CAN Controller, software has to set up the Bit Timing registers and the filter

banks. If a filter bank is not used, it is recommended to leave it non active (leave the

corresponding FACT bit in the CAN_FCRx register cleared).

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