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STM8S データシート(PDF) 388 Page - STMicroelectronics |
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STM8S データシート(HTML) 388 Page - STMicroelectronics |
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388 / 467 page ![]() Controller area network (beCAN) RM0016 388/467 DocID14587 Rev 14 If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 0b10). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 0b11). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message. Otherwise the next valid message received will cause a loss of message. Refer also to Section 23.6.4: Message storage. Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. The hardware signals the overrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost depends on the configuration of the FIFO: – If the FIFO lock function is disabled (RFLM bit in the CAN_MCR register cleared) the last message stored in the FIFO will be overwritten by the new incoming message. As a result, the last message is always available to the application. Note: The previously received messages will stay in their positions in the FIFO, only the last one will be overwritten. – If the FIFO lock function is enabled (RFLM bit in the CAN_MCR register set) the most recent message will be discarded and the software will have the three oldest messages in the FIFO available. Reception related interrupts On the storage of the first message in the FIFO - FMP[1:0] bits change from 0b00 to 0b01 - an interrupt is generated if the FMPIE bit in the CAN_IER register is set. When the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CAN_RFR register is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set. On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in the CAN_IER register is set. 23.6.3 Identifier filtering In the CAN protocol the identifier of a message is not associated with the address of a node but related to the content of the message. Consequently a transmitter broadcasts its message to all receivers. On message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. If the message is needed, it is copied into the RAM. If not, the message must be discarded without intervention by the software. To fulfil this requirement, the beCAN Controller provides 6 configurable and scalable filter banks (5:0) in order to receive only the messages the software needs. This hardware filtering saves CPU resources which would be otherwise needed to perform filtering by software. Each filter bank x consists of eight 8-bit registers, CAN_FxR[8:1]. |
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