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STM8S データシート(PDF) 412 Page - STMicroelectronics |
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STM8S データシート(HTML) 412 Page - STMicroelectronics |
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412 / 467 page  Controller area network (beCAN) RM0016 412/467 DocID14587 Rev 14 23.11.14 CAN bit timing register 2 (CAN_BTR2) Address offset: See Table 71. Reset value: 0x23 This register can only be accessed by the software when the CAN hardware is in initialization mode. 7 654 3210 Reserved BS2[2:0] BS1[3:0] r rwrw rw rwrw rw rw Bit 7 Reserved, must be kept cleared. Bits 6:4 BS2[2:0] Bit Segment 2 These bits define the number of time quanta in Bit Segment 2. Bit Segment 2 = (BS2+1) Bits 3:0 BS1[3:0] Bit Segment 1 These bits define the number of time quanta in Bit Segment 1 Bit Segment 1 = (BS1+1) For more information on bit timing, please refer to Section 23.6.6: Bit timing. |
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