ADC3541 datasheet(32/68 Pages) TI1

部品番号	ADC3541

部品情報	ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC

PDF	68 Pages

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メーカー	TI1 [Texas Instruments]

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7.3.4.5 Output Formatting with Decimation

7.3.4.5.1 Parallel CMOS

In parallel CMOS mode, the ADC354x device supports complex decimation output with DDR CMOS interface

and real output with SDR and DDR CMOS interface as shown in Figure 7-32 (complex decimation) and Figure

7-33 (real decimation). In this illustration the output format is selected to 16-bit.

D15..0

DCLK

Sample

D15

(MSB)

D14

Figure 7-32. Output Data Format in Complex Decimation

Table 7-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on

complex decimation setting (N).

Furthermore the table shows an actual lane rate example with complex decimation by 4.

Table 7-4. Parallel CMOS Data Rate Examples with Complex Decimation

REAL/COMPLEX

DECIMATION

SETTING

ADC SAMPLING RATE

DCLK

DOUT (MHz)

Complex

FS x 2 / N

FS x 4 / N

65 MHz

32.5 MHz

65 MHz

ADC3541

SBAS840 – JULY 2020

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ADC3541 データシート(PDF) 32 Page - Texas Instruments