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ADC3541 データシート(PDF) 13 Page - Texas Instruments

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部品番号 ADC3541
部品情報  ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
PDF  68 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3541 データシート(HTML) 13 Page - Texas Instruments

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PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
OUTPUT RATE: 10 MSPS
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
SDR CMOS
TBD
6.3
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
DDR CMOS
TBD
6.3
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
Serial CMOS: 2-wire
TBD
2.0
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
Serial CMOS: 1-wire
TBD
2.0
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
OUTPUT RATE: 25 MSPS
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
SDR CMOS
TBD
6.2
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
DDR CMOS
TBD
6.2
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
Serial CMOS: 2-wire
TBD
2.0
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
OUTPUT RATE: 65 MSPS
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
SDR CMOS
TBD
6.1
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
tPD
Propagation delay: sampling clock falling
edge to DCLK rising edge
DDR CMOS
TBD
6.1
ns
tCD
DCLK rising edge to output data delay
TBD
0.2
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
10
12
MHz
tSU(SEN)
SEN to rising edge of SCLK
TBD
ns
tH(SEN)
SEN from rising edge of SCLK
TBD
ns
tSU(SDIO)
SDIO to rising edge of SCLK
TBD
ns
tH(SDIO)
SDIO from rising edge of SCLK
TBD
ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD)
SDIO tri-state to driven
TBD
ns
t(ODZ)
SDIO data to tri-state
TBD
ns
t(OD)
SDIO valid from falling edge of SCLK
TBD
ns
www.ti.com
ADC3541
SBAS840 – JULY 2020
Copyright © 2020 Texas Instruments Incorporated
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