データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

STM32G071C8 データシート(PDF) 83 Page - STMicroelectronics

部品番号 STM32G071C8
部品情報  Arm Cortex-M0 32-bit MCU, up to 128 KB Flash, 36 KB RAM
PDF  133 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G071C8 データシート(HTML) 83 Page - STMicroelectronics

Back Button STM32G071C8 Datasheet HTML 79Page - STMicroelectronics STM32G071C8 Datasheet HTML 80Page - STMicroelectronics STM32G071C8 Datasheet HTML 81Page - STMicroelectronics STM32G071C8 Datasheet HTML 82Page - STMicroelectronics STM32G071C8 Datasheet HTML 83Page - STMicroelectronics STM32G071C8 Datasheet HTML 84Page - STMicroelectronics STM32G071C8 Datasheet HTML 85Page - STMicroelectronics STM32G071C8 Datasheet HTML 86Page - STMicroelectronics STM32G071C8 Datasheet HTML 87Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 83 / 133 page
background image
DS12232 Rev 3
83/133
STM32G071x8/xB
Electrical characteristics
106
Figure 22. I/O AC characteristics definition(1)
1. Refer to Table 53: I/O AC characteristics.
5.3.15
NRST input characteristics
The NRST input driver uses CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 21: General operating conditions.
MS32132V2
T
10%
50%
90%
10%
50%
90%
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by the specified capacitance.
r
f
r(IO)out
t
f(IO)out
t
Table 54. NRST pin characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low level
voltage
-
-
-
0.3 x VDDIO1
V
VIH(NRST)
NRST input high level
voltage
-
0.7 x VDDIO1
--
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
--
200
-
mV
RPU
Weak pull-up
equivalent resistor(2)
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST input filtered
pulse
--
-
70
ns
VNF(NRST)
NRST input not filtered
pulse
1.7 V ≤ VDD ≤ 3.6 V
350
-
-
ns
1.
Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order)
.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com