ISM303DAC datasheet(64/80 Pages) STMICROELECTRONICS

64 / 80 page

ISM303DAC

64/80

DocID030988 Rev 2

8.21

INT_DUR_A (32h)

Interrupt duration register (r/w)

Table 66. INT_DUR_A register

Table 67. INT_DUR_A register description

8.22

WAKE_UP_THS_A (33h)

Wakeup threshold register (r/w)

Table 68. WAKE_UP_THS_A register

Table 69. WAKE_UP_THS_A register description

LAT3

LAT2

LAT1

LAT0

QUIET1

QUIET0

SHOCK1

SHOCK0

LAT [3:1]

Duration of maximum time gap for double-tap recognition. When double-tap

recognition is enabled, this register expresses the maximum time between two

successive detected taps to determine a double-tap event.

1 LSB = 32 TODR.

QUIET [1:0]

Expected quiet time after a tap detection: this register represents the time after

the first detected tap in which there must not be any over-threshold event.

1 LSB = 4 TODR.

SHOCK [4:0]

Maximum duration of over-threshold event: this register represents the maximum

time of an over-threshold signal detection to be recognized as a tap event.

1 LSB = 8 TODR

SINGLE_

DOUBLE_

TAP

SLEEP_

WU_

THS_ 5

WU_

THS_4

WU_

THS_3

WU_

THS 2

WU_

THS 1

WU_

THS 0

SINGLE_

DOUBLE_

TAP

Double/single-tap event detection:

(0: double-tap event detection; 1: single-tap event detection)

SLEEP_ON

Sleep (inactivity) enable

(0: sleep disabled; 1: sleep enabled)

WU_THS [5:0]

Wakeup threshold

ISM303DAC データシート(PDF) 64 Page - STMicroelectronics

ISM303DAC データシート(HTML) 64 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

データシートダウンロード