AD9546SLASHPCBZ datasheet(114/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 114 of 205

The translation profiles control only the frequency translation

of the DPLL. The overall frequency translation of the channel

depends on the following:

•

N divider value (depending on the translation mode)

•

M divider value (via the APLL0 and APLL1 controls)

•

R divider value (via the REFx and auxiliary REFx controls)

•

Q divider value (via the distribution controls)

Each For detailed information on the use and programming of

the N, M, R, and Q divider values, see the DPLL Feedback

Divider (N Divider), APLL Feedback Divider (M Divider),

Reference Dividers (R Dividers), and Distribution Dividers (Q

Dividers) sections.

PROFILE ENABLE

For a DPLL channel to have access to a translation profile, the user

must enable the profile. To enable a translation profile, program

Bit 0 to Logic 1 (default is Logic 0) in the register at the start

address of the translation profile (per Table 74). Only enabled

translation profiles are selectable by the DPLL. When the DPLL

selects a translation profile, the selected translation profile

becomes an active translation profile (see the Reference

Switching section for what constitutes an active translation

profile). Certain functional blocks within the AD9546 make use

of the active and inactive state of a translation profile.

PROFILE PRIORITY

Profile priority works in conjunction with the reference switching

capability of the AD9546 (see the Reference Switching section).

The user programs a priority value via Bits[5:1] in the register at

the start address of the translation profile per Table 74. When a

DPLL must switch from one input reference to another, the

DPLL can do so according to the 5-bit priority value

programmed by the user. A priority of 0 constitutes the highest

priority, and a priority of 31 constitutes the lowest priority.

INPUT REFERENCE SOURCE SELECTION

The AD9546 provides the user with several options for the

reference source that supplies the input clock signal to the

DPLL. These options include any one of the four REFx inputs,

any of the four auxiliary REFx inputs, either of the two auxiliary

NCOs, either of the two inverse user time stampers, and a

special configuration that uses the feedback signal from the

other DPLL channel. Each translation profile can specify a

different reference source.

Source selection is via Bits[4:0] in the register at the start

address of the translation profile (see Table 74) plus an offset of

1 (decimal). The decimal value associated with Bits[4:0] assigns

the source, as shown in Table 75.

Table 75. Reference Source Selection

Bits[4:0]

Source

REFA

REFAA

REFB

REFBB

Feedback from DPLL0 (for PLL1 only)

Feedback from DPLL1 (for PLL0 only)

Auxiliary REF0

Auxiliary REF1

Auxiliary NCO 0

Auxiliary NCO 1

Not applicable

Auxiliary REF2

Auxiliary REF3

Inverse User Time Stamper 0

Inverse User Time Stamper 1

15 to 31

Not applicable

ACTIVE REFERENCE INDICATION

When a DPLL selects a translation profile, the translation

profile becomes active (see the Profile Enable section), which

causes the user assigned reference input (see the Input

Reference Source Selection section) associated with that profile

to become the time stamp source to the DPLL.

Note that when a reference becomes the time stamp source to a

DPLL, the reference becomes an active reference. The user has

access to the active or inactive state of a reference via an

appropriately configured Mx status pin.

In summary, indication of active reference status is the result of

a DPLL activating a translation profile (which contains a user

assigned reference source). As such, do not confuse the active

reference status with the valid reference status, which is a status

condition associated with the reference source itself (not a

translation profile).

AD9546/PCBZ データシート(PDF) 114 Page - Analog Devices

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