AD9546SLASHPCBZ datasheet(185/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 185 of 205

WATCHDOG TIMER

The watchdog timer is a general-purpose programmable timer

capable of triggering a specific IRQ event (see Figure 124). The

timer relies on the system clock, however. Therefore, the

system clock must be present and locked for the watchdog

timer to be functional. The bit fields associated with the watchdog

timer reside in the Mx pin status and control function section of

the register map.

The user sets the period of the watchdog timer via Bits[15:0] in

timeout value carries units of milliseconds and provides a range

of 1 ms to 65.535 sec.

A value of zero (default) disables the watchdog timer. The relative

accuracy of the timer is approximately 0.1% with an uncertainty

of 0.5 ms.

Updating the watchdog timer value automatically clears the

timer, ensuring a correct timeout period (per the new value)

starting from the moment of the update.

The 16-bit watchdog timer value relates to the timeout period

as follows:

Watchdog Timer Value = Timeout Period × 103

To determine the watchdog timer value necessary for a timeout

period of 10 sec,

Watchdog Timer Value = Timeout Period × 103

= 10 × 103

= 10,000

= 0x2710 (hexadecimal)

If enabled, the timer runs continuously and generates a timeout

IRQ event when the timeout period expires. The user has access

to the watchdog timer status as an IRQ bit (see the Interrupt

Request (IRQ) section) via Bit 2 of Register 0x300B.

Because Bit 2 of Register 0x300B is a latched IRQ bit, the user

must clear it via Bit 2 of Register 0x2006 to obtain visibility of

subsequent watchdog timeout events. The user also has access to

the watchdog timeout status by assigning the watchdog timer to

an Mx status pin. In this case, the timeout event of the

watchdog timer is a pulse spanning 96 system clock periods

(approximately 40 ns).

There are two ways to reset the watchdog timer, thereby

preventing it from indicating a timeout event. The first method

is by writing a Logic 1 to Bit 7 (an autoclearing bit) in Register

0x2005. Alternatively, the user can program any of the Mx pins

as a control pin to reset the watchdog timer, which allows the

user to reset the timer using a hardware pin rather than using

the register map.

There are two typical cases for employing the watchdog timer,

both of which assume the watchdog timer output appears at the

output of an appropriately configured Mx status pin. The first case

is for an external device (an FPGA or microcontroller, for

example) to monitor the watchdog timer output, using the

output as a signal to carry out periodic housekeeping functions.

The second case is to have the watchdog timer output

connected to the external device such that the assertion of the

watchdog output resets the external device. In this way, under

normal operation, the external device repeatedly resets the

watchdog timer by either writing Logic 1 to the clear watchdog

bit or by asserting an Mx control pin configured for clearing the

watchdog. Therefore, as long as the external device keeps

resetting the watchdog timer before the timer times out, the

watchdog timer does not generate an output signal. As such,

the watchdog timer does not reset the external device.

However, if the external device fails to reset the watchdog timer

before the timeout period expires, the watchdog timer

eventually times out, resetting the external device via the

appropriately configured Mx status pin.

TIMER

CLK

OUT

PRESET

CLEAR

Mx PIN FUNCTION LOGIC

Mx PINS

40ns

TO IRQ EVENT

SOURCE LOGIC

CLEAR

WATCHDOG VIA

Mx PIN

WATCHDOG

OUTPUT VIA

Mx PIN

INTERNAL

1kHz CLOCK

NOTE

1. A RANGE OF BITS USES A COLON SEPARATOR

REG 0x2005, BIT 7

REG 0x010B TO 0x010A, BITS[15:0]

Figure 124. Watchdog Timer

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