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データシートサーチシステム |
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データシートサーチシステム |
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P5021 データシート(PDF) 4 Page - NXP Semiconductors |
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P5021 データシート(HTML) 4 Page - NXP Semiconductors |
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4 / 155 page  P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Pin assignments and reset states Freescale Semiconductor 4 Figure 2. 1295 BGA ball map diagram (top view) LA 29 29 30 31 32 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 19 20 21 22 23 24 25 26 27 28 33 34 36 35 AJ AK AL AM W Y AA AB AC AD AE AF AG AH A B C D E F G H J K L M N P R T U V AN AP AR AT D2_ MDQ 20 D2_ MDQ 10 D2_ MDQS 1 D2_ MDQ 08 D2_ MDQ 03 D2_ MDQ 07 D2_ MDQ 04 D1_ MDQ 03 D1_ MDQ 06 D2_ MDQ 16 GVDD D2_ MDQ 17 D2_ MDM 1 D2_ MDQ 13 D2_ MDQ 02 D2_ MDM 0 D2_ MDQ 05 D1_ MDQ 07 D2_ MDQS 2 D2_ MDM 2 D2_ MDQ 14 D1_ MDQ 21 D2_ MDQ 22 D2_ MDQ 23 D2_ MDQ 18 D2_ MDQ 15 D2_ MDQ 09 D1_ MDQS 2 D1_ MDM 2 D1_ MDQ 17 D1_ MDQ 20 D2_ MDQ 00 D1_ MDQ 02 D1_ MDQ 08 D2_ MDQ 19 D2_ MDQ 29 D1_ MDQ 18 D1_ MDQ 19 D1_ MDQ 13 RSRV D2_ MDQ 24 D2_ MDQ 25 D1_ MDQ 24 D1_ MDQ 28 D1_ MDQ 25 D2_ MDM 3 D2_ MDQS 3 D1_ MDQ 11 D1_ MDQS 1 LAD 31 D2_ MDQ 31 D2_ MDQ 30 D2_ MDQ 26 D2_ MDQ 27 D1_ MDQ 30 D1_ MDQ 31 NC_ H15 D2_ MECC 5 D2_ MECC 4 D1_ MECC 5 D1_ MDQ 27 NC_ J14 LAD 15 D2_ MDM 8 D1_ MDM 8 D1_ MECC 0 NC_ K14 LAD 14 D2_ MECC 6 D2_ MECC 7 D1_ MECC 6 D1_ MECC 7 D2_ MCKE 3 D2_ MECC 02 D1_ MBA 2 D2_ MECC 3 D2_MA 09 D2_ MCKE 2 D2_MA 06 D2_MA 08 D2_MA 07 D2_ MCKE 0 D2_MA 03 D2_MA 04 D2_MA 05 D1_MA 01 D1_MA 02 D1_MA 03 D1_MA 04 D1_ MDM 0 D1_ MDQ 00 D2_ MDQ 06 D1_ MDQS 0 D1_ MDQ 05 D2_ MDQ 12 D1_ MDQS 0 D1_ MDQ 04 D1_ MDM 1 D1_ MDQ 22 D1_ MDQ 10 GVDD GND GVDD GND GVDD GND GND GVDD GVDD GND GVDD GND GND GVDD GND GVDD GVDD GND GVDD NC_ E16 GND GND GVDD NC_ D18 LA 28 GND GVDD D1_ MDQ 29 GND GVDD D1_ MDQ 15 GND D1_ MDQ 12 GVDD GND D1_ MDQS 3 GVDD GND D1_ MDQ 09 GVDD GVDD GND GVDD GND NC_ H12 NC_ H13 GVDD BVDD GND GVDD D1_ MECC 4 GND NC_ J11 GVDD NC_ J13 LAD 13 D2_ MECC 1 GVDD D1_ MDQS 8 GND GVDD NC_ K11 NC_ K12 NC_ K13 SENSE- VDD_CA SENSE- GND_CA GVDD GND GVDD VDD_PL GND VDD_PL VDD_PL VDD_PL GND GND GND D2_ MBA 2 GND GVDD GND GND VDD_PL GND GND GND VDD_PL VDD_CA VDD_CA D2_MA 12 D2_MA 14 GVDD GND GVDD VDD_PL VDD_PL VDD_CA VDD_CA GND GND GND GND GVDD GND GVDD D1_ MCKE 0 GND VDD_PL GND GND GND VDD_CA VDD_CA VDD_CA GND GVDD D1_MA 07 GND VDD_PL VDD_PL VDD_CA VDD_CA GND GND GND GND GVDD D1_ MDIC 0 GND D1_MA 06 GVDD GND VDD_PL GND GND GND VDD_PL VDD_CA VDD_CA GVDD GND GVDD VDD_PL VDD_PL VDD_PL VDD_PL GND GND GND GND GVDD GND GND VDD_PL GND GND GND VDD_PL VDD_PL VDD_PL D2_ MDQ 21 SD_RX 16 TMS TMS PD GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL NC_ W27 SD_TX 12 SD_TX 12 XGND SD_RX 12 SD_RX 12 SGND SVDD GND GND GND GND GND VDD_PL VDD_PL VDD_PL GND XGND SD_TX 13 SVDD SGND SD_RX 13 SD_RX 13 GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL SD1_IMP_ CAL_TX XVDD SD_TX 14 SD_RX 14 SD_RX 14 SGND GND GND GND GND GND VDD_PL VDD_PL VDD_PL GND SD_TX 18 SD_TX 18 SD_TX 15 XGND SGND SVDD AVDD_ SRDS3 AGND_ SRDS3 GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL VDD_ LL S1VDD XVDD GND GND GND GND VDD_PL VDD_PL VDD_PL VDD_PL GND VDD_ LP XGND SD_ REF_ CLK3 SD_ REF_ CLK3 SGND SVDD VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND SD_RX 18 SVDD SGND GND GND GND GND VDD_PL VDD_PL VDD_PL SD_RX 19 SGND SD_RX 19 SD1_IMP CAL_RX SD_RX 16 SVDD SGND DMA2_ DACK 0 GPIO 07 OVDD PD SD_TX 19 S1VDD RSRV X1VDD SD_TX 19 IO_ VSEL 4 MSRCID 0 GPIO 04 GND USB1_ AGND USB1_ VDD_ USB2_ VDD_ USB2_ AGND SPI_ MISO SD_PLL4 _TPD GND EMI2_ MDIO EMI2_ MDC MSRCID 1 DMA2_ DREQ 0 GPIO 05 OVDD USB1_ AGND USB1_ VDD_ USB2_ VDD_ USB2_ VDD_ SPI_CS 1 CVDD GND EMI1_ MDC LVDD GND CLK_ OUT GPIO 06 GPIO 01 USB1_ UID USB1_ VBUS_ USB2_ VBUS_ USB2_ UID GND SPI_ CLK LVDD DMA1_ DACK 0 OVDD GPIO 00 SHDC_ USB1_ VDD_ USB1_ IBIAS_ GND LVDD EMI1_ MDIO EC2_ GTX_ GND TSEC_ 1588_CLK _IN SDHC_ GND GPIO 02 CKSTP_ OUT USB_ CLKIN USB1_ VDD_1P8 SPI_CS 3 GND EC1_ RXD 03 LVDD OVDD DMA1_ DDONE 0 GPIO 03 TMP_ DETECT RTC SPI_CS 0 GND PD 12 PD 06 LVDD EC1_ RXD 2 EC1_ RXD 1 EC1_ RXD 0 GND DMA2_ DDONE 0 DMA1_ DREQ 0 GND PD 14 CVDD PD 02 LVDD PD 07 PD 05 GND EC1_ GTX_ CLK EC1_ TXD 3 TRST ASLEEP TCK OVDD AVDD_ FM SPI_CS 2 PD 03 PD 09 GND EC1_ RX_DV PD 10 EC1_ TXD 1 LVDD EC1_ TX_EN AVDD_ PLAT TEST_ SEL GND SYSCLK PD 15 SPI_ MOSI PD 04 PD 01 PD 08 PD 11 EC1_ TXD 2 EC1_ TXD 0 GND EC1_ RX_CLK EC_XTRNL _TX_STMP 2 EC_XTRNL _RX_STMP 2 TSEC_ 1588_CLK_ OUT TSEC_ 1588_PULSE _OUT01 TSEC_ 1588_PULSE _OUT2 EC_XTRNL _TX_STMP 1 TSEC_ 1588_ALARM _OUT2 TSEC_ 1588_ALARM _OUT1 TSEC_ 1588_TRIG _IN2 TSEC_ 1588_TRIG _IN1 SD_IMP_ CAL_TX LA 19 LAD 11 GND LA 28 AVDD_ DDR MVREF LBCTL LCS 5 LCS 00 LCS 1 LA 21 LA 22 LAD 04 SD_TX 03 LAD 07 LAD 06 LA 29 LA 20 LA 18 LAD 05 LAD 03 LA 26 LA 23 GND LA 24 GND XGND AVDD_ SRDS4 SD_RX 04 SD_RX 05 SD_RX 05 SGND SGND SD_RX 08 SD_RX 09 SD_RX 09 SD_RX 10 SD_RX 10 AVDD_ CC1 LALE AVDD_ SRDS1 AGND_ SRDS1 SD_ REF_ CLK1 SD_ REF_ CLK1 LCS 3 LCS 4 LWE 0 LCS 2 LWE 1 NC_ C19 NC_ C20 GND GND GND GND LCLK 1 LCLK 0 LAD 09 BVDD LGPL 0 LGPL 4 LGPL 2 GND NC_ C26 NC_ C27 NC_ D27 SGND SVDD SD_RX 00 SD_RX 00 SD_RX 01 SD_RX 01 SGND SVDD SVDD SD_RX 03 SD_RX 03 SGND XGND SD_RX 02 SVDD SD_RX 02 SGND SD_TX 04 XGND BVDD LAD 08 BVDD LGPL 1 LGPL 5 NC_ E27 XGND SD_TX 03 XVDD XVDD SGND SVDD LAD 12 BVDD GND LCS 6 BVDD GND SD_TX 01 SVDD LA 25 LA 17 LCS 7 NC_ G27 XVDD SVDD BVDD LGPL 3 NC_ H27 XGND XGND SD_RX 06 SD_RX 06 GND LAD 10 GND LDP 0 LA 16 LAD 02 SD_TX 06 XGND SGND SVDD LA 27 BVDD LDP 1 BVDD LAD 00 XVDD SD_TX 07 SD_TX 07 SVDD SD_RX 07 SD_RX 07 VDD_PL VDD_PL GND VDD_PL VDD_PL GND GND LAD 01 SENSE- GND_PL 2 SENSE- VDD_PL 2 XVDD XGND SD_RX 08 SVDD SGND GND GND GND GND VDD_CA VDD_PL VDD_PL VDD_PL GND XVDD XGND SD_TX 08 SD_TX 08 SVDD SGND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL SD_TX 09 SD_TX 09 XVDD SGND SVDD GND GND GND GND VDD_CA VDD_PL VDD_PL VDD_PL GND XGND XVDD SD_TX 10 SD_TX 10 VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL XVDD XGND SVDD SGND GND GND GND GND VDD_CA VDD_PL VDD_PL VDD_PL GND AGND_ SRDS4 XVDD SGND AVDD_ SRDS2 AGND_ SRDS2 VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_ REF_ XGND SGND GND GND GND GND VDD_PL VDD_PL VDD_PL VDD_PL GND SD_ XGND XVDD SGND SVDD XVDD SD_IMP_ CAL_RX 29 30 31 32 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 19 20 21 22 23 24 25 26 27 28 33 34 36 35 AJ AK AL AM W Y AA AB AC AD AE AF AG AH A B C D E F G H J K L M N P R T U V AN AP AR AT D2_ MDQ 48 D1_ MDQ 54 D1_ MDQ 50 D2_ MDQ 56 D2_ MDQ 58 D2_ MDQS 6 D2_ MDQ 54 D2_ MDQS 7 D1_ MDQ 62 D1_ MDQ 59 D2_ MDQ 55 D2_ MDQ 61 D2_ MDQ 57 D2_ MDQ 63 D2_ MDQ 59 D1_ MDQ 56 D1_ MDQS 7 D1_ MDQ 58 D2_ MCK 0 D1_ MCK 0 D2_ MDIC 1 D2_ MCS 0 D1_ MDQ 33 D1_ MDQ 32 D2_ MODT 2 D2_ MODT 0 D1_ MDM 4 D1_ MODT 0 D2_ MODT 3 D2_ MDQ 37 D1_ MDQ 35 D2_ MDM 4 D2_ MDQ 32 D1_ MDQ 45 D1_ MDQ 44 D1_ MODT 1 D2_ MDQ 38 D1_ MDQS 5 D1_ MDM 5 D2_ MDQ 35 D2_ MDQ 34 D1_ MDQ 42 D2_ MDQ 45 D2_ MDQ 44 D1_ MDQ 53 D2_ MDM 5 D2_ MDQ 41 D2_ MDQ 40 D1_ MDQ 49 D1_ MDM 6 D2_ MDQ 52 D2_ MDQS 5 D2_ MDQ 46 D1_ MDQS 6 D1_ MCK 0 GND D1_ MCK 3 D1_ MCK 3 GVDD VDD_PL VDD_PL GND GND GND GND GND GND GND GVDD D1_ MBA 1 GND VDD_PL GND GND GND VDD_PL GND GND D2_ MAPAR_ OUT D1_ MDIC 1 GVDD GND VDD_PL VDD_PL GND GND GND GND GND GND D2_ MRAS GVDD GND GVDD GND VDD_PL GND GND GND GND GND GND GVDD D2_MA 13 GND GVDD D1_ MCS 0 VDD_PL VDD_PL GND GND GND GND GND GND GND GVDD D1_ MODT 2 GND GND VDD_PL GND GND GND VDD_PL VDD_PL VDD_PL D1_ MDQ 39 GND GVDD VDD_PL VDD_PL VDD_PL VDD_PL GND GND GND GND D2_ MODT 1 GVDD GND GVDD D1_ MCS 3 SENSE- VDD_PL 1 SENSE- GND_PL 1 GND GND GND VDD_PL VDD_PL VDD_PL GND D1_ MDQ 40 GVDD GND IIC4_ SCL NC_ AG15 GND IRQ 06 D2_ MDQS 4 GVDD D1_ MDQS 5 GND GVDD GND IRQ 10 IIC1_ SCL IRQ 01 IRQ 04 GVDD D2_ MDQ 39 GND D1_ MDQ 46 GVDD GND OVDD IRQ 05 OVDD IRQ 03 IRQ 00 EVT 0 OVDD GND GVDD GND IRQ 09 IRQ 02 IIC3_ SCL IRQ_ OUT GND EVT 3 EVT 1 IO_ VSEL 2 GVDD GND D1_ MDQ 48 GVDD IRQ 11 GND IIC2_ SDA IIC4_ SDA OVDD SCAN_ MODE IO_ VSEL 0 GVDD GND GVDD GND IRQ 07 IIC3_ SDA IIC2_ SCL EVT 4 GND IO_ VSEL 3 D2_ MDQ 53 GND D2_ MDQ 42 D2_ MDQ 43 GVDD D1_ MDQ 55 GND D1_ MDQ 51 GVDD IIC1_ SDA GND EVT 2 TDI OVDD D2_ MDM 6 D2_ MDQ 49 GVDD D2_ MDM 7 GND D1_ MDQ 60 GVDD GND TDO OVDD PORESET IO_ VSEL 1 GVDD D2_ MDQ 60 GND D2_ MDQ 62 GVDD D1_ MDQ 61 D1_ MDQ 57 GND GVDD MDVAL GND GND HRESET D2_ MDQ 51 D2_ MDQS 7 OVDD RESET_ REQ POVDD GVDD AVDD_ CC2 D2_ MDQS 1 D2_ MDQS 0 D2_ MDQS 0 D2_ MDQ 01 D2_ MDQ 11 D2_ MDQS 2 D1_ MDQ 16 D1_ MDQS 2 D1_ MDQ 01 GND D2_ MDQ 28 D1_ MDQ 23 D1_ MDQ 14 D1_ MDQS 1 D2_ MDQS 3 D1_ MDQS 3 D1_ MDM 3 D1_ MDQ 26 D2_ MECC 0 D1_ MECC 1 D2_ MDQS 8 D1_ MDQS 8 D1_MA 15 D1_ MECC 2 D2_MA 15 D1_MA 14 D1_ MECC 3 D2_ MAPAR_ ERR D1_MA 12 D1_ MAPAR_ ERR D1_ MCKE 3 D2_MA 11 D1_MA 09 D1_MA 11 D1_ MCKE 2 D1_MA 08 D1_ MCKE 1 D2_ MCKE 1 D1_MA 05 GND D2_MA 01 D2_MA 02 D2_ MCK 2 D1_ MCK 1 D2_ MCK 2 D2_ MCK 1 D2_ MCK 1 D1_ MCK 1 D1_ MCK 2 D1_ MCK 2 D2_ MCK 3 D2_ MCK 3 D2_ MCK 0 GVDD GND D2_MA 00 D1_ MAPAR_ OUT D1_MA 00 D2_ MBA 1 D2_MA 10 D2_ MBA 0 D2_ MDIC 0 D1_MA 10 D1_ MBA 0 D1_ MRAS D2_ MWE D2_ MCS 2 D1_ MDQ 36 D1_ MDQ 37 D1_ MWE D1_ MCS 2 D2_ MCAS D1_ MCAS D1_ MDQS 4 D1_ MDQS 4 D2_ MCS 1 D2_ MCS 3 D1_ MDQ 38 D1_MA 13 D1_ MCS 1 D2_ MDQ 36 D1_ MDQ 34 D1_ MODT 3 D2_ MDQ 33 D2_ MDQS 4 D1_ MDQ 41 MSRCID 2 GND D1_ MDQ 47 D1_ MDQ 43 D1_ MDQ 52 GVDD D2_ MDQS 5 D2_ MDQ 47 D1_ MDQS 6 VID_ VDD_CA VID_ VDD_CA D2_ MDQS 6 TEST_ SEL2 D1_ MDQ 63 VID_ VDD_CA D2_ MDQ 50 D1_ MDM 7 D1_ MDQS 7 VID_ VDD_CA NC_ A27 SVDD SGND NC_ B26 SGND SVDD SGND SVDD SVDD SD_RX 04 SGND SVDD SGND XGND SD_TX 01 SD_TX 04 XVDD SD_TX 05 XVDD SD_TX 00 XGND XGND SD_TX 05 SGND SD_TX 00 SD_TX 02 SD_TX 02 XVDD XGND XVDD LA 30 XVDD XGND XVDD SD_TX 06 GND XGND XGND XVDD XGND XGND XGND XVDD XGND XVDD XGND SGND SVDD SD_TX 11 SD_TX 11 XVDD SD_RX 11 SD_RX 11 XGND XVDD SVDD XGND XVDD SD_ REF_ CLK2 SD_ REF_ CLK2 XVDD SD_TX 13 XVDD XGND XGND SD_TX 14 SVDD SD_TX 15 XVDD XVDD XGND SD_RX 15 SD_RX 15 XGND XGND XVDD XVDD SD_TX 16 SD_TX 16 XVDD XGND XGND SD_TX 17 SD_TX 17 SGND SVDD SD_RX 17 SD_RX 17 UART2_ CTS UART2_ SOUT UART2_ RTS UART1_ SOUT UART1_ RTS UART2_ SIN UART1_ CTS UART1_ SIN D2_ MDQS 8 SEE DETAIL A SEE DETAIL B XGND XVDD SGND SGND SVDD EC_XTRNL _RX_STMP 1 RSRV _AD34 SD_RX 18 RSRV _AD33 RSRV _AG11 RSRV _AG12 RSRV _A25 RSRV _AH12 RSRV _AH11 SEE DETAIL C OVDD I/O Supply Voltage LVDD I/O Supply Voltage Local Bus I/O Supply SerDes Core Power Supply SVDD SerDes Transcvr Pad Supply XVDD DDR DRAM I/O Supply GVDD BVDD Platform Supply Voltage VDD_ PL VDD_ CA Core Group A Supply Voltage AVDD_ SRDS1 SerDes 1 PLL Supply Voltage AVDD_ SRDS2 SerDes 2 PLL Supply Voltage CVDD SPI Voltage Supply Platform Voltage Sense SENSE- VDD_PL SENSE- VDD Core Group A Voltage Sense SENSE- VDD_CB Core Group B Voltage Sense Platform PLL Supply Voltage Core PLL Supply Voltage AVDD_ CC AVDD_ PLAT Reserved Signal Groups Fuse Programming Override Supply POVDD RSRV 17 13 CLK DAT RSRV LA 31 RSRV RSRV GND LDP 3 LDP 02 _F1 _F2 _G1 _G2 LA 30 LWE 2 LWE 3 IRQ 08 RSRV _AK1 RSRV _AK2 RSRV _AL1 RSRV _AL2 RSRV _A21 TEMP_ CATH- ODE TEMP_ ANODE RSRV _L28 RSRV _N28 RSRV _P28 LP_TMP _DETECT RSRV _U35 RSRV _U32 CVDD 1P0 1P0 3P3 3P3 3P3 CLMP CLMP 2 EC2_ RX_ER 3P3 USB1_ AGND _DECAP USB2_ VDD_1P8 _DECAP USB1_ AGND CLK125 USB1_ AGND REXT USB2_ IBIAS_ REXT USB2_ AGND USB2_ AGND USB2_ AGND USB2_ AGND USB2_ AGND USB2_ AGND USB2_ AGND USB2_ AGND USB1_ AGND USB1_ AGND USB1_ AGND USB1_ AGND USB1_ UDP USB1_ UDM USB2_ UDM USB2_ UDP USB2_ AGND RSRV _C32 RSRV _D32 EC1_ GTX_ CLK125 LAD 27 CLK4 REF_ CLK4 SEE DETAIL D _CB3 _CB2 _CB1 _CB0 _AG29 RSRV _M28 |
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