P5021 datasheet(84/155 Pages) NXP

84 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

This figure shows the Ethernet management interface timing diagram.

Figure 19. Ethernet management interface timing diagram

2.12.4

eTSEC IEEE Std 1588 timing specifications

This section discusses the electrical characteristics for the eTSEC IEEE Std 1588 interfaces.

2.12.4.1

TSEC IEEE Std 1588 DC electrical characteristics

This table shows eTSEC IEEE Std 1588 DC electrical characteristics when operating at LVDD = 3.3 V supply.

MDIO to MDC hold time

tMDDXKH

0—

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or

data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach

the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock

frequency of the MgmtClk Clock EC_MDC).

3. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data

clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns.

Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

VIH

2.0

—

Input low voltage

VIL

—0.9

Input high current (LVDD = Max, VIN = 2.1 V)

IIH

—40

μA1

Table 41. Ethernet management interface 2 AC timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Note

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

P5021 データシート(PDF) 84 Page - NXP Semiconductors

P5021 データシート(HTML) 84 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード