MPC8347ECVRADDB datasheet(79/99 Pages) NXP

部品番号	MPC8347ECVRADDB

部品情報	MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Clocking

19.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 60 shows the multiplication factor

encodings for the system PLL.

As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 61

3 The DDR data rate is 2× the DDR memory bus frequency.

4 The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the

csb_clk frequency (depending on RCWL[LBIUCM]).

Table 60. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication Factor

0000

× 16

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111

× 7

1000

× 8

1001

× 9

1010

× 10

1011

× 11

1100

× 12

1101

× 13

1110

× 14

1111

× 15

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