MMPF0200Z datasheet(28/118 Pages) NXP

28 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

6.4

Power Generation

6.4.1

Modes of Operation

The operation of the PF0200Z can be reduced to five states, or modes: ON, OFF, Sleep, Standby, and Coin Cell. Figure 8 shows

the state diagram of the PF0200Z, along with the conditions to enter and exit from each state.

Figure 8. State Diagram

To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must

exceed the rising UVDET threshold to allow a power up. Refer to Table 27 for the UVDET thresholds. Additionally, I2C control is

not possible in the Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states.

6.4.1.1

ON Mode

The PF0200Z enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

PWRON = 0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON=1

& VIN > UVDET

(PWRON_CFG =0)

PWRON= 0 < 4.0 sec

& VIN > UVDET

(PWRON_CFG=1)

PWRON = 0

Any SWxOMODE bits=1

(PWRON_CFG=0)

PWRON=0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON=1

& VIN > UVDET

(PWRON_CFG = 0)

PWRON= 0 < 4.0 sec

& VIN > UVDET

(PWRON_CFG=1)

PWRON = 0

All SWxOMODE bits= 0

(PWRON_CFG = 0)

PWRON = 0 held >= 4.0 sec

All SWxOMODE bits= 0

& PWRONRSTEN = 1

(PWRON_CFG = 1)

OFF

Sleep

Coin Cell

VIN < UVDET

VIN > UVDET

Thermal shudown

Standby

STANDBY asserted

VIN < UVDET

Thermal shutdown

STANDBY de-asserted

PWRON = 0

Any SWxOMODE bits=1

(PWRON_CFG=0)

PWRON=0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON = 0

All SWxOMODE bits= 0

(PWRON_CFG = 0)

PWRON = 0 held >= 4.0 sec

All SWxOMODE bits= 0

& PWRONRSTEN = 1

(PWRON_CFG = 1)

VIN < UVDET

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