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MMPF0200Z データシート(PDF) 7 Page - NXP Semiconductors

部品番号 MMPF0200Z
部品情報  12 Channel Configurable Power Management Integrated Circuit
PDF  118 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0200Z データシート(HTML) 7 Page - NXP Semiconductors

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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
PF0200Z
Pin Connections
Pin Definitions
3.2
Pin Definitions
Table 2. PF0200Z Pin Definitions
Pin Number
Pin Name
Pin
Function
Max Rating
Type
Definition
1
INTB
O
3.6 V
Digital
Open drain interrupt signal to processor
2
SDWNB
O
3.6 V
Digital
Open drain signal to indicate an imminent system shutdown
3
RESETBMCU
O
3.6 V
Digital
Open drain reset output to processor. Alternatively can be used
as a Power Good output.
4
STANDBY
I
3.6 V
Digital
Standby input signal from processor
5
ICTEST
I
7.5 V
Digital/
Analog
Reserved pin. Connect to GND in application.
6SW1FB (4)
I
3.6 V
Analog
Output voltage feedback for SW1A/B. Route this trace separately
from the high-current path and terminate at the output
capacitance.
7SW1AIN (4)
I
4.8 V
Analog
Input to SW1A regulator. Bypass with at least a 4.7
F ceramic
capacitor and a 0.1
F decoupling capacitor as close to the pin as
possible.
8
SW1ALX (4)
O
4.8 V
Analog
Regulator 1A switch node connection
9
SW1BLX (4)
O
4.8 V
Analog
Regulator 1B switch node connection
10
SW1BIN (4)
I
4.8 V
Analog
Input to SW1B regulator. Bypass with at least a 4.7
F ceramic
capacitor and a 0.1
F decoupling capacitor as close to the pin as
possible.
11
RSVD1
-
-
Reserved
Reserved for pin to pin compatibility. Internally connected. Leave
this pin unconnected.
12
RSVD2
-
-
Reserved
Reserved for pin to pin compatibility. Connect this pin to VIN.
13
RSVD3
-
-
Reserved
Reserved for pin to pin compatibility. Internally connected. Leave
this pin unconnected.
14
SW1VSSSNS
GND
-
GND
Ground reference for regulator SW1AB. It is connected externally
to GNDREF through a board ground plane.
15
GNDREF1
GND
-
GND
Ground reference for regulator SW2. It is connected externally to
GNDREF, via board ground plane.
16
VGEN1
O
2.5 V
Analog
VGEN1 regulator output, Bypass with a 2.2
F ceramic output
capacitor.
17
VIN1
I
3.6 V
Analog
VGEN1, 2 input supply. Bypass with a 1.0
F decoupling
capacitor as close to the pin as possible.
18
VGEN2
O
2.5 V
Analog
VGEN2 regulator output, Bypass with a 4.7
F ceramic output
capacitor.
19
RSVD4
-
-
Reserved
Reserved for pin to pin compatibility. Internally connected. Leave
this pin unconnected.
20
RSVD5
-
-
Reserved
Reserved for pin to pin compatibility. Connect this pin to VIN
21
RSVD6
-
-
Reserved
Reserved for pin to pin compatibility. Internally connected. Leave
this pin unconnected.
22
SW2LX (4)
O
4.8 V
Analog
Regulator 2 switch node connection
23
SW2IN (4)
I
4.8 V
Analog
Input to SW2 regulator. Connect pin 23 together with pin 24 and
bypass with at least a 4.7
F ceramic capacitor and a 0.1 F
decoupling capacitor as close to these pins as possible.
24
SW2IN (4)
I
4.8 V
Analog



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